Align the container to the disc, and find the decoder-free packed player fits

Two sessions, unrecorded until now, committed together because their edits
share files and cannot be split cleanly after the fact.

Session 28 (FINDINGS 60): the container is DLX5 -- every record sector-aligned,
120/120 starting on a boundary where 3/120 did, +0.48% on the wire and zero
clocks -- and the ring's release rounds to RECALN so no pad is stranded.  Two
encoder levers measured and refused: `--spans all` buys +0.19 dB for +67% of
the wire, and joint span/lam selection emits byte-identical containers because
`lam` never leaves its floor on any of 120 frames.

Session 29 (FINDINGS 61): the packed full-frame blit is 27.3% of a 12 fps
frame, a channel fills GVRAM in buffer mode off the disc with the CPU halted,
and it walks the 1,024 B line stride itself through array chaining.  At the
9 clk/B dual-address floor the codec is 110.4% of a frame and a decoder-free
packed literal player is 55.2%, at +4.89 dB -- 2.75 dB past a ceiling the
codec's scene-wide palette cannot cross.  Encoder work is parked; the codec is
kept and not built on.

check.sh is ALL GREEN before and after, plus one new stage that gates the ORDER
of the measured paint costs rather than their values.

Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6

src/player/dma.i

@@ -67,6 +67,8 @@ DM_CCR  = DMACB+$07                     ; channel control
 DM_MTC  = DMACB+$0A                     ; memory transfer count, WORD
 DM_MAR  = DMACB+$0C                     ; memory address, LONG
 DM_DAR  = DMACB+$14                     ; device address, LONG
+DM_BTC  = DMACB+$1A                     ; base transfer count, WORD (array chain)
+DM_BAR  = DMACB+$1C                     ; base address, LONG    (array chain)
 DM_MFC  = DMACB+$29
 DM_CPR  = DMACB+$2D
 DM_DFC  = DMACB+$31
@@ -113,6 +115,17 @@ DM_CERF  = $18518                       ; u32 CER with it
 DM_MTCF  = $1851C                       ; u32 MTC with it
 DM_MARF  = $18520                       ; u32 MAR with it -- where it stopped
 DM_LEN   = $18524                       ; u32 bytes the channel was asked for
+; ---- SEQUENTIAL ARRAY CHAINING, and it is OFF unless a caller asks for it.
+; A device->GVRAM transfer cannot be one contiguous run: a picture row is 256 B
+; of a 1024 B line stride, so 192 rows want 192 destinations.  The MC68450 walks
+; an array of 6-byte {u32 MAR, u16 MTC} entries for exactly this, and MAME's
+; hd63450 implements it (`(ocr & 0x0c) == 0x08`, dma_transfer_start and
+; dma_transfer_continue).  DM_BARV = 0 means no chaining and NOTHING below
+; changes, which is what stream.s gets: this file is included by the player as
+; well as by the gate, and a mailbox that defaults to a new behaviour is how
+; DM_USE landed on ring.i's slot and turned a stage red (above).
+DM_BARV  = $18528                       ; u32 array base address, 0 = no chain
+DM_BTCV  = $1852C                       ; u32 array entry count (BTC)
 DM_PATIENCE = 4000000                   ; the wait is bounded like every other
 
 ; ---------------------------------------------------------------- sc_in_dma
@@ -144,8 +157,20 @@ sc_in_dma:
         move.b  #$05,DM_MFC             ; the function codes the IPL ROM uses
         move.b  #$05,DM_DFC
         move.b  #$01,DM_CPR
+        move.l  DM_BARV.l,d0
+        bne.s   .chain
         move.w  d5,DM_MTC
         move.l  a1,DM_MAR
+        bra.s   .darset
+.chain:
+        ; MAR and MTC are NOT written: the channel loads both from the array's
+        ; first entry when it starts, and reloads them from the next entry at
+        ; every count-out.  Writing them here would be writing registers the
+        ; hardware is about to overwrite, which reads like a contract and is not.
+        move.l  d0,DM_BAR
+        move.l  DM_BTCV.l,d0
+        move.w  d0,DM_BTC
+.darset:
         move.l  #SC_DREG,DM_DAR         ; $EA0015 -- the DMAC's door, and now
                                         ; the DMAC is the one going through it
         move.b  #SCMD_XFER,SC_SCMD      ; no PROGRAM bit: the SPC raises DRQ