Pace the ring, then read the DMAC config out of the IPL ROM: audio is cheap and the disk is not

Two sessions that were never separated in the working tree, so they land as one
commit. check.sh ALL GREEN before and after both.

SESSION 19 -- the ring rig gets a frame clock (FINDINGS 51).

src/player/stream.s had no frame clock: it asked for record i the instant it
finished i-1, outran any finite pipe, and never let the ring back up. The 49.1
sweep passing at 48 KB was therefore a wrap-correctness result and nothing else.
PACE/PACEON ($18034/$18038) hold the decoder to 12 fps, so FR_HEAD-FR_TAIL
finally means what it reads as: whole frames the decoder could still draw with
delivery stopped dead. PACEON=0 free-runs and is what the wrap gate still uses,
so every figure in 49 is unmoved.

Paced, on the gate container: 64 KB holds 2 frames, 256 KB holds 7-8, 512 KB
holds 14-15, all pixel-exact. Tolerance is ceiling-1, measured by cutting the
pipe: 256 KB buys 500 ms of dead pipe, not 583.

SLACK IS ACCUMULATED, NOT OWNED. It is built out of pipe-wire and a seek spends
all of it. At 488 KB/s a 256 KB ring needs 4.83 s of play to reach its ceiling
from empty; 512 KB needs 8.42 s to reach 14. A bigger ring raises the ceiling
AND lengthens the climb, so a branch point does not ask "is the buffer big
enough" but "has there been enough play since the last one" -- and Dragon's
Lair's decision points are seconds apart. The rig now also says WHICH resource
is binding: at 460 KB/s every ring from 192 KB to 512 KB is rate-bound at
ceiling 4 and never fills, so larger rings are dead RAM in that scene.
20_seek_slack.py is the same model rewritten in Python from record sizes,
sharing no code with the Lua producer: 35/35 ceilings inside its bracket.

SESSION 20 -- the DMAC configuration was in the IPL ROM the whole time
(FINDINGS 52).

ROADMAP's "do this first" was to put the ADPCM stream on the bus. That needs a
clocks-per-byte figure for the audio channel, and 11_cpu_budget.py was charging
audio the DISK's rate -- 5 clk/B, its own help text calling it "single-address,
bus held". Audio was being charged the favourable end of B3, a 242 KB/s open
question.

It never had to be a guess. The IPL ROM programs all four HD63450 channels
itself and MAME boots the rig with it, so 21_iplrom_dmac.py reads the
configuration out of the image and decodes the MC68450 fields. Eight
(address, expected bytes, meaning) sites; a mismatch or an unknown revision
exits non-zero. In check.sh, no emulator, milliseconds.

ch3 DCR=$80, OCR=$32: dual address, 8-bit port, cycle steal WITHOUT hold,
REQG=10 external request. The DMAC arbitrates once per byte with no burst to
amortise the 5..8 + 2 over, so an audio byte is 16..19 clocks, not 5 -- the old
debit was 3.2x..3.8x small. And on the bus it is still nothing: 651 B/frame is
1.25%..1.48% of a frame, about 4% of what the decoder leaves. P6's bus risk
does not materialise. The unit worry was worth checking and nearly right: 15.6
kHz is 8 MHz/512 = 15,625 samples/s, two 4-bit samples to a byte = 7,812.5 B/s
exactly, and AUDIO_KBPS=7.8 is that in decimal kB while the tool multiplied by
1024.

THE DISK CHANNEL IS PROGRAMMED IDENTICALLY. ch1 (SASI) is DCR=$80 too, and so
is ch0. That is 16..19 clocks per delivered byte, where 42.4 brackets W at 5..12
and 42.5 has W=8 already missing 47/120 frames. The only worked example of a
disk DMA configuration on this machine sits above the entire bracket, and at
that price nothing fits at any container size. It is not scsiexrom.bin so B3
stays open -- what changed is that a cheap configuration is now the thing that
has to be SHOWN. W <= 12 is a requirement on the player's DMAC programming, not
a range the hardware hands us, and it is now the largest open number in the
project, ahead of the rate.

An unforced cross-check fell out: 15_bus_occupancy.py's new W sweep puts W=8 at
105.7% of the frame, agreeing with 42.5's 47/120, from mode histograms and bus
clocks respectively, two models sharing no code.

Also: ADPCM outranks the disk at the arbiter (CPR 1 against 2), so an audio byte
never waits and a video byte does -- relevant to 51's smooth-rate delivery model.

README MEDIA.

stream.lua gains DLX_SNAP_EVERY=1 (needs DLX_PACE, off by default, on no path
check.sh takes) and tools/media/make_readme_media.py turns the PNGs into
docs/img/. The stills and both clips are MAME's own screen pixels.

Building it turned up something worth recording. 116 of 119 captured frames are
pixel-exact against dlx.py; three are TORN -- frame n on top, frame n-1 below
the tear line -- because MAME captured the screen while the block loop was
partway down it. decode.s writes straight to the displayed page (one display
path, 28.1), so a real player tears the same way, and this is the first time
that consequence has been visible rather than argued. The script ASSERTS the
tear and refuses to build otherwise, rather than trimming three frames and
reporting "every frame I kept is exact". Second correction the capture forced:
the snapshot fires before frame n is decoded, so the obvious reading is that it
holds frame n-1 -- it does not, because MAME renders the screen at the end of
the machine frame, by which time the 68000 has finished frame n.

11_cpu_budget.py's "validated to within 1 pt" line is also corrected: the model
reads 2..10 pt HIGH and by more as the frame gets harder, which was already true
before either session.

src/player/decode.s is unchanged; decode.bin is still 1,296 B at the same MD5.

Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6

docs/BENCHMARK.md

@@ -53,13 +53,31 @@ was used. **Do not record KB/s and treat it as a hardware figure.**
 Already partly in FINDINGS 5. Bounds worth tightening from datasheets:
 
 - 68000 bus cycle: 4 clocks @ 10MHz, 16-bit  => **5 MB/s** absolute ceiling
-- HD63450 single-address DMA, ~8 clocks/word => **~2.5 MB/s** practical ceiling
+- HD63450 single-address DMA, **5 clocks/BYTE** => **2.0 MB/s** practical ceiling
+  (dual-address is 9 clocks/byte => 1.11 MB/s). CORRECTED session 14: this line
+  read "~8 clocks/word => ~2.5 MB/s", which charged a byte-wide SPC per word.
+  FINDINGS 43.
 - SCSI-1 asynchronous REQ/ACK handshake per byte, plus MB89352 FIFO depth
   => the real limiter, and the number we do not have from a primary source
 
-The user's working figure is **4 Mbps = 488 KB/s**, which sits sensibly between
-the derived DMA ceiling and observed period-drive rates. **Provenance not yet
-recorded — worth pinning down, because every profile now hangs off it.**
+**RETIRED, session 18 (USER DECISION).** This document used to name a working
+figure of "4 Mbps" here and note that every profile hung off it. It was never a
+bus measurement — user-supplied, no provenance, and 10% of SCSI-1's asynchronous
+rating (FINDINGS 42.1). It has been removed as a default from every analysis
+tool and from `tools/bench/stream.lua`; the tools now REQUIRE an explicit rate,
+so nothing can be scored against a figure the scorer never restates.
+
+**There is no working delivery figure. That is the honest state, and it is the
+point:** the rate is a property of the medium, the medium is a BlueSCSI, and it
+has not been measured. `tools/analysis/19_ring_stream.py` reports the
+**zero-prefill pipe** — the rate a medium must clear for a given container to
+need no prefill at all — which is the threshold a measurement should be taken
+against. For the session-14 candidate that is **513.2 KB/s** (FINDINGS 49.5).
+
+One place still carries the old number: `GATE_SPAN_KBPS` in
+`tools/bench/check.sh`, because the gate container was *encoded* with it and
+every per-block and span constant in FINDINGS 41/43/45/49 is fitted to that
+container. It is a container recipe, not a claim about any medium.
 
 ### The coupling nobody had counted
 Cycle-stealing DMA is not free DMA. At ~8 clocks per 16-bit word:
@@ -69,7 +87,7 @@ Cycle-stealing DMA is not free DMA. At ~8 clocks per 16-bit word:
 | 110 KB/s | 4.5% | 42.8% |
 | 250 KB/s | 10.2% | 48.5% |
 | 450 KB/s | 18.4% | 56.7% |
-| 488 KB/s | 20.0% | 58.3% |
+| ~490 KB/s | 20.0% | 58.3% |
 
 FINDINGS 5 concluded that because transfers are DMA, "streaming costs
 essentially no CPU". **That is wrong.** It costs up to a fifth of the machine at