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Put the data phase on the DMAC, and find auto-request is charged by time

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ROADMAP P4a. src/player/dma.i programs HD63450 channel 1 and takes the SCSI DATA
IN phase off the CPU; src/player/dmagate.s reads the same 2,048 B at LBA 1000
three ways -- PIO, the channel with the bus held, the channel stealing cycles --
and all three are byte-exact against the host's copy of the volume.

The evidence never reads $EA0015, because 57.3 established that it cannot: with
the DMAC's OWN asserted MAME cannot tell a CPU-driven byte there from a
DMAC-driven one. The discriminator is the CPU's own progress. MTC is sampled by
the INSTRUCTION AFTER the one that starts the channel, and held it reads 0 of
2,048 -- the whole transfer happened between two instructions, because the 68000
did not execute in between -- against the full count and 426 loop trips for the
stealing configuration. Put the stealing registers in the held slot and every
byte still arrives and tools/bench/dma_run.sh goes RED, which is what says the
counter can come out different; 58.3's vacuous "UNDERRUNS: 0/120" is the trap
being avoided. tools/analysis/27_dmac_config.py decodes the four register bytes
out of the player's own source, with the MC68450 field tables now in one copy
(tools/analysis/mc68450.py) shared with 21_iplrom_dmac.py, so the player's
configuration and the IPL ROM's 16..19 clk/B one are the same decoding.

Three bounds on the apparatus, read out of MAME 0.277 rather than inferred: the
CZ-6BS1 has NO request line to the DMAC (its flow control is DTACK), so external
request cannot be run; single address cannot be run either, because only channel
0 has device callbacks; and only burst is modelled as held. Of the four rows of
the W ladder exactly one -- dual address held -- has a code path here, and it is
the one demonstrated. W did not move by one clock, for the third session running.

What outlives the emulator is the currency. Every W in this project is clocks per
DELIVERED byte, which presumes the device asks; an auto-requested channel spends
its share of the bus whether or not a byte is there, so a record costs what it
costs to ARRIVE -- halve the delivery rate and the CPU cost of the same record
doubles. tools/analysis/28_autorequest_cost.py prices it from MC68450 3.8 and
5.2.3.3.2, gating its formulas against Table 5-3's sixteen rows first. At 37,405
B and an explicit 460 KB/s: max rate costs the whole 95.3% of a frame the record
takes to land, and of the GCR's four bus shares only BR=00, 50%, carries the
rate -- 10.61 clk/B, 47.6% of a frame, against 40.4% for the W=9 row and 391.8%
measured for PIO. The GCR is a design lever nothing in this tree had named.

59.4 changes what is left. sc_in_data now REFUSES a windowed read when the data
phase is the channel's (SCE_WINDOW), because a channel writes a contiguous run
and cannot drop the 300 B in front of a record. 117 of 120 records need one, so
sector-aligned records have gone from a preference in ROADMAP's re-encode bundle
to the precondition the transport enforces -- and that bundle is now the only
thing between this tree and M2.

One collision, recorded because the procedure is the finding: DM_USE first sat at
$18300, which is ring.i's XF_SLOT mailbox, and the P4b stage -- untouched by this
work -- went red on a run that never reached its snapshot. check.sh was ALL GREEN
before any of this, which is what made that red unambiguous. ALL GREEN after too,
with one new stage. decode.bin is unchanged at 1,296 B and the same MD5.

Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6
This commit is contained in:
prosolis
2026-08-24 23:55:07 -07:00
parent 5921fab118
commit 621a5bb457
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@@ -5539,3 +5539,195 @@ now worth 87 against either.
**Does put a real number on the layer below every previous delivery result.**
Everything in FINDINGS 49, 51 and 55 was measured with the bytes arriving free.
They are not free, and 58.2 is the first measurement of what they cost.
---
## FINDINGS 59 — the DMAC drives the data phase, and auto-request is charged by time (session 27)
**Emulated.** MAME 0.277, `x68000 -exp1 cz6bs1 -ramsize 2M`, a blank
`scsiexrom.bin` on a private rompath (57.1's substitution, unchanged). No real
hardware ran. `./tools/bench/check.sh` was ALL GREEN before this and ALL GREEN
after, with one new stage.
**ROADMAP P4a is DONE at the transport level.** What is left before M2 is not a
DMAC question any more; it is the re-encode bundle, because 59.4 makes
sector-aligned records a precondition the transport now enforces rather than a
preference the roadmap recorded.
### 59.1 The channel drives the data phase, and the evidence is the CPU's own progress
`src/player/dma.i` programs HD63450 channel 1 and hands it the DATA IN phase;
`src/player/dmagate.s` reads **the same 2,048 B at LBA 1000 three ways** and the
host compares all three against its own copy of the image:
| | bytes | MTC one instruction after START | CPU trips round its wait loop |
|---|---|---|---|
| PIO, the path 58.2 measured | byte-exact | — | — |
| **DMA, bus HELD** (DCR `$00`, OCR `$81`) | **byte-exact** | **0 of 2048** | **1** |
| **DMA, cycle STEALING** (DCR `$80`, OCR `$80`) | **byte-exact** | 2048 of 2048 | 426 |
Both channels reported `CSR = $E0` (COC, BTC, NDT), `CER = $00`, `MTC = 0` and a
memory address exactly `+2048` from where it started.
**THE DISCRIMINATOR NEVER READS `$EA0015`, and that is the whole design.** 57.3
established that watching the data register cannot answer this question: with
the DMAC's `OWN` asserted — which it is at idle on this machine — MAME cannot
tell a CPU-driven byte there from a DMAC-driven one. So what separates the two
configurations is **whether the 68000 executed anything while the bytes were
arriving**:
move.b #CCR_START,DM_CCR ; the channel is told to go
move.w DM_MTC,d0 ; <- sampled by the VERY NEXT instruction
Held, `d0` is **zero**: the entire 2,048-byte transfer happened between two
instructions, because the CPU did not run in between. Stealing, `d0` is the full
count and the CPU then goes round its own loop 426 times while the bytes
trickle in. That is what "holds the bus" means, and it is a fact about the CPU
rather than about the data register.
**The mechanism, named so the claim is not over-read.** MAME models a held bus
by asserting `INPUT_LINE_HALT` for burst + max-rate and clearing it at
end-of-transfer (`hd63450.cpp`). It is not inventing that semantic: MC68450
§5.2.3.3.1 says of maximum-rate auto-request that "all operands in the data
block will be transferred in one burst, so that the DMAC will use **100% of the
available bus bandwidth**". The model and the datasheet agree about what this
configuration does to the CPU. **They do not agree about anything per-operand,
and no `W` is claimed here** (42.5: MAME's DMAC runs on wall-clock attotimes).
**The gate was checked against its own negative.** With the *stealing* register
pair put in the *held* slot, the run still delivers all 2,048 bytes byte-exact
— and `tools/bench/dma_run.sh` goes **red**, on the trip count and on the MTC
sample. A counter that cannot come out different is 58.3's vacuous
"UNDERRUNS: 0/120" again; this one can, and was made to.
`tools/analysis/27_dmac_config.py` decodes the four register bytes out of
`src/player/dma.i` itself, with the same MC68450 field tables
`21_iplrom_dmac.py` reads the IPL ROM with (now one copy, `mc68450.py`). So
"dual address, 8-bit port, burst, auto-request at max rate" is a decode of the
bytes the player programs, not a comment next to them — and it is directly
comparable with Sharp's own disk channel, which 52.5 read as `DCR $80 / OCR $B2`
and priced at 16..19 clk/B.
### 59.2 Three things this model cannot be asked, and they bound the result
Read out of MAME 0.277's source rather than inferred from behaviour:
1. **The card has no request line to the DMAC.** `x68k_scsiext.cpp`'s `drq_w`
only stores a flag; the expansion slot carries no request to the HD63450 at
all (`x68k.cpp` wires `drq0` from the FDC and `drq3` from ADPCM, and nothing
else). The card's flow control is **DTACK**: on a DMAC cycle with DRQ low it
negates DTACK and the channel discards that operand and retries. So **REQG =
10, external request — the mode the ladder's `W`=5 and `W`=12 rows assume —
cannot be run here at all.**
2. **Single address cannot be run either.** `hd63450.cpp` takes the implicit
path only for a channel with a device callback, and on this machine only
channel 0 (the FDC) has one. `DTYP` = 10/11 on channels 1..3 falls through to
the dual-address code.
3. **Only burst is modelled as held.** The device tests `(dcr & 0xc0) == 0`, so
XRM = 10 (cycle steal *without* hold) and XRM = 11 (cycle steal **with**
hold) are one code path.
**So of the four rows of the per-byte ladder, exactly one — dual address, bus
held, 9 clk/B — has a code path in this model, and it is the one demonstrated.**
That is a bound on the apparatus, not a result about the board. The slot's own
pinout has `#EXREQ` at B36, so a real CZ-6BS1 plausibly drives it; whether it
does is ROADMAP B3, and it is now a sharper question than "which DTYP".
### 59.3 Auto-request is charged by TIME, not by byte — and the GCR is the lever
This is the finding that outlives the emulator. Every `W` in this project is
**clocks per delivered byte**, which presumes the device asks for each one. An
auto-requested channel does not know whether the device is ready: it takes the
share of the bus it was told to take and spends it either way. So the cost of a
record scales with **how long the record takes to arrive** — halve the delivery
rate and the CPU cost of the same record **doubles**. No `W` does that.
`tools/analysis/28_autorequest_cost.py` prices it from MC68450 §3.8 and
§5.2.3.3.2, and gates its formulas against Table 5-3's sixteen printed rows
before printing anything. At the gate container's 37,405 B mean record and
**460 KB/s, an explicit rate and not a measurement** (FINDINGS 50):
| configuration | sustains | charged to the 68000 | % of a 12 fps frame |
|---|---|---|---|
| REQG 01, max rate — what 59.1 demonstrated | the wire | 21.23 clk/B | **95.3%** |
| REQG 00, LRAR, BR = 00, 50% of the bus | 534 KB/s | 10.61 clk/B | **47.6%** |
| REQG 00, LRAR, BR = 01, 25% | 267 KB/s | 5.31 | 23.8% — **does not carry the rate** |
| REQG 00, LRAR, BR = 10, 12.5% | 133 KB/s | 2.65 | 11.9% — **does not carry the rate** |
| *(ladder, for comparison)* `W`=9 dual held | — | 9 | 40.4% |
| *(measured, 58.2)* PIO | — | 87.28 | 391.8% |
**The held configuration is the cheapest per byte MOVED and the dearest per byte
DELIVERED**, and the gap between those two is the device's own slowness: 9
clocks of DMAC work inside 21.2 clocks of waiting means **42.4% of the held bus
does anything at all**. Holding the bus is only cheap when the hold is ended by
the device, which is what external request is for.
**BT and BR are two bits each and they set what fraction of the bus the player
gives away** (burst time `2^(BT+4)` clocks, sample period `2^(BT+BR+5)`, share
`2^-(BR+1)`). Nothing in this tree had named the GCR as a design choice; it is
the same kind of lever as `aligned` vs `split` and it belongs in the same list.
**At 460 KB/s only BR = 00 carries the rate**, so the fallback plan — if a real
card turns out not to drive `#EXREQ` — is 50% of the bus for the duration of
every record, or 47.6% of a frame slot per record. That is affordable and it is
not free, and it is the first cost model in this project that gets *worse* when
the disc gets slower.
**59.3's one load-bearing assumption**, stated because the whole table rests on
it: that the channel *spends* its allotted share whether or not the device has a
byte. Under auto-request a request is pending until MTC is exhausted, so the
DMAC takes the bus during every window it is entitled to; when the device is not
ready the cycle is stretched by wait states (a real card negating DTACK) or
retried later (MAME's model discards the operand), and either way the window is
gone from the CPU's point of view. **If a real CZ-6BS1 instead lets the DMAC off
the bus early when no byte is there, 59.3's figures are upper bounds.** That is
a board question, and it is B3's.
### 59.4 The window is refused, and that makes the re-encode a precondition
58.3 found that 117 of 120 records start part way into a sector, and that PIO
absorbs it for free because the CPU is already touching every byte. A channel
cannot: it writes a contiguous run and cannot be told to drop the 300 bytes in
front of the record. `sc_in_data` now **refuses** a windowed read when the data
phase is the DMAC's — a new error, `SCE_WINDOW` — rather than quietly delivering
the neighbouring records' bytes into the ring, where the block loop has no
bounds check to catch them (49.2). The gate asserts the refusal.
**So "sector-aligned records" has stopped being a preference in ROADMAP's
re-encode bundle and become the thing standing between P4a and the ring.** The
transport states its own precondition; the container does not meet it yet.
### 59.5 What this does and does not move
**Does not move `W`.** Not by one clock, for the third session running, and for
the reason 57.6 and 58.4 give.
**Does not put the DMAC behind `ring.i`'s mailbox.** 59.4 is why: `xfer.i` asks
for records, and every record but three needs a window. That work is now
downstream of the re-encode bundle rather than of a DMAC question.
**Does close the question ROADMAP called P4's first job.** A configuration that
holds the bus exists, runs, delivers the disc's bytes byte-exact, and is
demonstrated by evidence that does not come from watching `$EA0015` — which is
exactly what 57.3 said would be needed.
**Does change what the fallback looks like.** Before this session the fallback
below a held bus was `W` = 16..19, the IPL ROM's own arbitrated configuration.
It is now limited-rate auto-request at a share the player chooses, priced in a
currency the project did not have, and the arithmetic says a 50% share carries
this container at 460 KB/s.
### 59.6 One collision, and it was caught by the half of `check.sh` that runs first
`DM_USE` — the word that tells `sc_in_data` whether the data phase is the
DMAC's — was first placed at `$18300`. `scsi.i`'s trace ends at `$182FF` and the
next 160 bytes are the **ring's**: `$18300` is `ring.i`'s `XF_SLOT` mailbox, and
`tools/bench/stream.lua` reads the same addresses from outside the machine. So
the ring rig's first record request wrote a non-zero word into what the
transport now read as "use the DMAC", and **the P4b stage — a stage this session
did not otherwise touch — went red on a run that never reached its snapshot.**
Recorded because the procedure is the finding: `check.sh` was ALL GREEN before
any of this work, so the red was unambiguously new, and the failure was in a
stage nobody would have re-run on suspicion. Both halves of "green before and
green after" earned their place; the map is now `$18500`, clear of everything
the streaming rig owns.