Put the data phase on the DMAC, and find auto-request is charged by time
ROADMAP P4a. src/player/dma.i programs HD63450 channel 1 and takes the SCSI DATA IN phase off the CPU; src/player/dmagate.s reads the same 2,048 B at LBA 1000 three ways -- PIO, the channel with the bus held, the channel stealing cycles -- and all three are byte-exact against the host's copy of the volume. The evidence never reads $EA0015, because 57.3 established that it cannot: with the DMAC's OWN asserted MAME cannot tell a CPU-driven byte there from a DMAC-driven one. The discriminator is the CPU's own progress. MTC is sampled by the INSTRUCTION AFTER the one that starts the channel, and held it reads 0 of 2,048 -- the whole transfer happened between two instructions, because the 68000 did not execute in between -- against the full count and 426 loop trips for the stealing configuration. Put the stealing registers in the held slot and every byte still arrives and tools/bench/dma_run.sh goes RED, which is what says the counter can come out different; 58.3's vacuous "UNDERRUNS: 0/120" is the trap being avoided. tools/analysis/27_dmac_config.py decodes the four register bytes out of the player's own source, with the MC68450 field tables now in one copy (tools/analysis/mc68450.py) shared with 21_iplrom_dmac.py, so the player's configuration and the IPL ROM's 16..19 clk/B one are the same decoding. Three bounds on the apparatus, read out of MAME 0.277 rather than inferred: the CZ-6BS1 has NO request line to the DMAC (its flow control is DTACK), so external request cannot be run; single address cannot be run either, because only channel 0 has device callbacks; and only burst is modelled as held. Of the four rows of the W ladder exactly one -- dual address held -- has a code path here, and it is the one demonstrated. W did not move by one clock, for the third session running. What outlives the emulator is the currency. Every W in this project is clocks per DELIVERED byte, which presumes the device asks; an auto-requested channel spends its share of the bus whether or not a byte is there, so a record costs what it costs to ARRIVE -- halve the delivery rate and the CPU cost of the same record doubles. tools/analysis/28_autorequest_cost.py prices it from MC68450 3.8 and 5.2.3.3.2, gating its formulas against Table 5-3's sixteen rows first. At 37,405 B and an explicit 460 KB/s: max rate costs the whole 95.3% of a frame the record takes to land, and of the GCR's four bus shares only BR=00, 50%, carries the rate -- 10.61 clk/B, 47.6% of a frame, against 40.4% for the W=9 row and 391.8% measured for PIO. The GCR is a design lever nothing in this tree had named. 59.4 changes what is left. sc_in_data now REFUSES a windowed read when the data phase is the channel's (SCE_WINDOW), because a channel writes a contiguous run and cannot drop the 300 B in front of a record. 117 of 120 records need one, so sector-aligned records have gone from a preference in ROADMAP's re-encode bundle to the precondition the transport enforces -- and that bundle is now the only thing between this tree and M2. One collision, recorded because the procedure is the finding: DM_USE first sat at $18300, which is ring.i's XF_SLOT mailbox, and the P4b stage -- untouched by this work -- went red on a run that never reached its snapshot. check.sh was ALL GREEN before any of this, which is what made that red unambiguous. ALL GREEN after too, with one new stage. decode.bin is unchanged at 1,296 B and the same MD5. Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6
This commit is contained in:
prosolis
@@ -0,0 +1,211 @@
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; The HD63450 driving the SCSI data phase. ROADMAP P4a.
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;
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; WHAT P4a HAS TO SHOW, and why it needed a new kind of evidence. FINDINGS 58
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; measured the CPU moving every byte itself at 87.28 clocks per delivered byte
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; -- 391.8% of a 12 fps frame, against 22.4% for the cheapest DMA row of the
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; ladder and 85.3% for the dearest. So the whole of what is left before M2 is a
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; DMAC configuration that HOLDS THE BUS. 57.3 is why it could not simply be
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; watched into existence: x68k_scsiext.cpp glues $EA0015 so that with the DMAC's
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; OWN asserted -- which it is at idle on this machine -- MAME CANNOT DISTINGUISH
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; a CPU-driven byte at that address from a DMAC-driven one. Watching the data
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; register cannot answer the question it looks like it answers.
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;
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; THE DISCRIMINATOR USED HERE IS THE CPU'S OWN PROGRESS, and it never reads
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; $EA0015 at all. A DMAC that holds the bus is one the CPU is not running
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; against; so the witness is a single instruction:
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;
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; move.b #CCR_START,DM_CCR ; the channel is told to go
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; move.w DM_MTC,d0 ; <- sampled by the VERY NEXT instruction
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;
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; If the bus was held for the transfer, the whole transfer happened between
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; those two instructions and d0 reads ZERO. If it was not, d0 reads very nearly
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; the full count and the CPU goes on to spin thousands of times while the
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; channel trickles. Both configurations deliver the same bytes; what separates
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; them is whether the 68000 got to execute anything meanwhile, which is exactly
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; what "holds the bus" means and is not a fact about $EA0015.
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;
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; WHAT MAME CAN AND CANNOT BE ASKED, stated here because it bounds the claim and
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; it is not obvious from the outside:
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;
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; * THE CARD HAS NO EXREQ PATH. x68k_scsiext.cpp's drq_w only stores a flag;
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; the expansion slot has no request line to the DMAC at all (x68k.cpp wires
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; drq0 from the FDC and drq3 from ADPCM, and nothing else). The card's flow
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; control is DTACK: on a DMAC cycle with DRQ low the card NEGATES DTACK and
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; the HD63450 discards that operand and retries. So every configuration
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; below is AUTO-REQUEST; REQG=10, external request -- the mode the ladder's
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; W=5 and W=12 rows assume -- has no wiring in this model and cannot be run.
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; * SINGLE ADDRESS CANNOT BE RUN EITHER. hd63450.cpp only takes the implicit
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; path when a channel has a dma_read/dma_write callback, and on this machine
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; only channel 0 (the FDC) has one. DTYP=10/11 on channels 1..3 falls
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; through to the dual-address code.
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; * ONLY BURST IS MODELLED AS HELD. The device tests `(dcr & 0xc0) == 0`, so
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; XRM=10 (cycle steal without hold) and XRM=11 (cycle steal WITH hold) are
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; one code path. The bus is held, and the CPU halted, only for XRM=00 burst
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; with REQG=01 max rate.
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;
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; So of the four rows of the per-byte ladder, exactly ONE -- dual address, bus
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; held, 9 clk/B -- has a code path in this model, and it is the one demonstrated
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; below. That is a bound on the apparatus and not a result about the board.
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;
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; AND IT IS STILL NOT A RATE. MAME's DMAC is configured in wall-clock attotimes
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; (42.5), not per-operand cycles: set_burst_clocks gives channel 1 450 ns an
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; operand no matter what the 68000 is doing. `W` is untouched by every line in
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; this file and still wants a board (ROADMAP B1/B3).
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; ---- the channel. 1, not 0: channel 0 is the FDC's and is the one channel
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; with device callbacks, which would silently take the implicit-address path.
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; Channel 1 is also the channel the IPL ROM points at the SASI data register
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; (52.5), so this is the machine's own disk channel programmed differently.
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DMA_CH = 1
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DMACB = DMAC+DMA_CH*DMAC_CH ; $E84040
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DM_CSR = DMACB+$00 ; channel status (write 1s to clear)
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DM_CER = DMACB+$01 ; channel error (read only)
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DM_DCR = DMACB+$04 ; device control
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DM_OCR = DMACB+$05 ; operation control
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DM_SCR = DMACB+$06 ; sequence control
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DM_CCR = DMACB+$07 ; channel control
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DM_MTC = DMACB+$0A ; memory transfer count, WORD
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DM_MAR = DMACB+$0C ; memory address, LONG
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DM_DAR = DMACB+$14 ; device address, LONG
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DM_MFC = DMACB+$29
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DM_CPR = DMACB+$2D
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DM_DFC = DMACB+$31
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; CSR bits
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CSR_COC = $80 ; channel operation complete
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CSR_BTC = $40
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CSR_NDT = $20 ; normal device termination
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CSR_ERR = $10 ; channel error -- CER says which
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CSR_ACT = $08 ; channel active
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CCR_START = $80
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; ---- the two configurations, as (DCR, OCR) pairs. Both are decoded by
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; tools/analysis/27_dmac_config.py out of THESE bytes, using the same MC68450
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; field tables 21_iplrom_dmac.py reads the IPL ROM's channels with -- so what
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; the run claims it programmed and what it programmed cannot drift apart.
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;
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; HELD : DCR $00 = XRM 00 burst, DTYP 00 dual address, DPS 0 8-bit port
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; OCR $81 = DIR device->memory, SIZE byte, no chain, REQG 01 max rate
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; STEAL: DCR $80 = XRM 10 cycle steal WITHOUT hold, otherwise identical
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; OCR $80 = REQG 00 auto-request at limited rate
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DM_HELD_DCR = $00
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DM_HELD_OCR = $81
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DM_STEAL_DCR = $80
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DM_STEAL_OCR = $80
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; ---- what the run reports. Every one of these is a DMAC register or a count
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; of the CPU's own instructions; none of them is a read of $EA0015.
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; $18500 AND NOT $18300, WHICH IS WHERE THIS FIRST WENT. scsi.i's trace ends at
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; $182FF and the next 160 bytes are the RING's: $18300 is ring.i's XF_SLOT
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; mailbox, and tools/bench/stream.lua reads the same addresses from outside.
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; dma.i is included by stream.s as well as by the gate, so DM_USE landed on the
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; transfer request slot and the ring rig's first record request read as "use the
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; DMAC" -- P4b's stage went red on a run that never reached its snapshot. The
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; symptom was in a stage this session did not touch, which is the whole argument
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; for check.sh being run before and after rather than only after.
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DM_USE = $18500 ; u32 0 = PIO data phase, 1 = this file
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DM_DCRV = $18504 ; u32 the DCR byte to program
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DM_OCRV = $18508 ; u32 the OCR byte to program
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DM_MTC0 = $1850C ; u32 MTC one instruction after START
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DM_SPIN = $18510 ; u32 times the CPU went round the wait
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DM_CSRF = $18514 ; u32 CSR when the channel finished
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DM_CERF = $18518 ; u32 CER with it
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DM_MTCF = $1851C ; u32 MTC with it
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DM_MARF = $18520 ; u32 MAR with it -- where it stopped
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DM_LEN = $18524 ; u32 bytes the channel was asked for
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DM_PATIENCE = 4000000 ; the wait is bounded like every other
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; ---------------------------------------------------------------- sc_in_dma
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; Receive d1 bytes into (a1) in phase d2, WITHOUT the CPU touching one of them.
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; Entered from sc_in_data when DM_USE is set; same registers, same contract.
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;
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; ORDER MATTERS AND IT IS NOT THE OBVIOUS ONE. The SPC is put into DMA transfer
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; BEFORE the channel is started, because in the held configuration the 68000
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; stops executing at the CCR write and does not run again until the transfer is
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; over -- so anything the SPC needs to be told has to have been told already.
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sc_in_dma:
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movem.l d3-d5,-(sp)
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move.l d1,d5 ; keep the length for the report
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move.l d5,DM_LEN.l
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move.b d2,SC_PCTL
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move.l d1,d0
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bsr sc_settc ; the SPC counts the same bytes down
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; ---- the channel, quiet first: CSR is write-one-to-clear and a stale
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; COC from a previous record would pass the wait loop instantly.
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move.b #$FF,DM_CSR
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move.l DM_DCRV.l,d0
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move.b d0,DM_DCR
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move.l DM_OCRV.l,d0
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move.b d0,DM_OCR
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move.b #$04,DM_SCR ; MAC 01 memory increment, DAC 00 none:
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; the device address is a REGISTER and
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; must not walk off it.
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move.b #$05,DM_MFC ; the function codes the IPL ROM uses
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move.b #$05,DM_DFC
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move.b #$01,DM_CPR
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move.w d5,DM_MTC
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move.l a1,DM_MAR
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move.l #SC_DREG,DM_DAR ; $EA0015 -- the DMAC's door, and now
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; the DMAC is the one going through it
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move.b #SCMD_XFER,SC_SCMD ; no PROGRAM bit: the SPC raises DRQ
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move.l #11,SC_TAG.l ; 11 = channel armed, SPC in DMA mode
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bsr sc_snap
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; ---- START, and the witness immediately after it
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move.b #CCR_START,DM_CCR
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move.w DM_MTC,d0 ; THE DISCRIMINATOR. Held: zero.
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andi.l #$FFFF,d0
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move.l d0,DM_MTC0.l
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; ---- wait for the channel, counting the CPU's own trips round the loop.
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; In the held configuration this is one trip, because the CPU did not
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; get to run until the transfer was over. In the stealing one it is
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; thousands, and every one of them is a 68000 instruction that executed
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; while the disc was delivering -- which is the whole point of P4a.
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clr.l DM_SPIN.l
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move.l #DM_PATIENCE,d3
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.wait: addq.l #1,DM_SPIN.l
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move.b DM_CSR,d4
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btst #4,d4 ; ERR
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bne.s .err
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btst #7,d4 ; COC
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bne.s .fin
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subq.l #1,d3
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bne.s .wait
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bsr .report
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movem.l (sp)+,d3-d5
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move.l #SCE_TIMEOUT,SC_ERR.l
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moveq #-1,d0
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rts
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.err: bsr .report
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movem.l (sp)+,d3-d5
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move.l #SCE_TIMEOUT,SC_ERR.l ; a channel error is a dead transport
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moveq #-1,d0
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rts
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.fin: bsr .report
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move.b #$FF,DM_CSR ; leave the channel as we found it
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move.l #12,SC_TAG.l ; 12 = channel reported COC
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bsr sc_snap
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movem.l (sp)+,d3-d5
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bsr sc_xferend ; the SPC's own transfer, not the DMAC's
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move.l d0,-(sp)
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move.l #9,SC_TAG.l
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bsr sc_snap
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move.l (sp)+,d0
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rts
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; ---- the channel's own account of what it did, read out of its registers
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.report:
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moveq #0,d0
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move.b DM_CSR,d0
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move.l d0,DM_CSRF.l
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moveq #0,d0
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move.b DM_CER,d0
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move.l d0,DM_CERF.l
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move.w DM_MTC,d0
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andi.l #$FFFF,d0
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move.l d0,DM_MTCF.l
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move.l DM_MAR,d0
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move.l d0,DM_MARF.l
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rts
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@@ -0,0 +1,132 @@
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; Front-end for the HD63450 DATA PHASE (ROADMAP P4a), for the rig.
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;
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; THE QUESTION. FINDINGS 58 put the transport on the 68000 and priced it: the
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; CPU moving every byte itself costs 87.28 clocks per delivered byte, 391.8% of
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; a 12 fps frame. Against that, the cheapest DMA row of the ladder is 22.4% and
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; the dearest is 85.3%, so everything left before M2 turns on getting the DMAC
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; to drive the data phase with the bus HELD. 57.3 is why it cannot be shown by
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; watching the data register: with the DMAC's OWN asserted, which it is at idle
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; here, MAME cannot tell a CPU-driven byte at $EA0015 from a DMAC-driven one.
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;
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; THE EVIDENCE THIS GATE PRODUCES, and none of it is a read of $EA0015:
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;
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; 1. THE SAME BYTES. The same sectors are read three times -- once by the PIO
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; path FINDINGS 58 measured, once by the channel with the bus held, once by
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; the channel stealing cycles -- and the HOST compares all three against its
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; own copy of the image. A transport that returns the wrong bytes without
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; saying so is the failure a checksum-free ring cannot survive (49.2).
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; 2. THE CPU'S OWN PROGRESS. MTC is sampled by the INSTRUCTION AFTER the one
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; that starts the channel. Held, it reads zero: the entire transfer
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; happened between two instructions, because the 68000 did not execute in
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; between. Stealing, it reads nearly the full count and the CPU then goes
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; round its wait loop thousands of times while the bytes arrive. That
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; difference IS "the DMAC held the bus", and it is a fact about the CPU.
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; 3. THE CHANNEL'S OWN ACCOUNT. CSR, CER, the final MTC and the final MAR:
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; the channel says it completed without error, moved every byte, and left
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; its memory pointer exactly one transfer-length past where it started.
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; 4. THE WINDOW IS REFUSED. A windowed read (58.3: 117 of 120 records start
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; part way into a sector) is rejected by the transport rather than silently
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; delivering the neighbouring records' bytes into the ring. P4a's
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; precondition is stated by the code that has it, not by a comment.
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;
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; WHAT IT DOES NOT SHOW. Not `W`. Not one clock of it. MAME's DMAC runs on
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; wall-clock attotimes (42.5) and its burst mode halts the CPU outright rather
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; than costing it cycles per operand, so this gate settles WHICH CONFIGURATION
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; WORKS and not what one costs. See src/player/dma.i for the three ways this
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; model bounds the question -- no EXREQ wiring, no single-address path, and only
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; burst modelled as held.
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DGFLAG = $18600 ; 0 idle / 1 done
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DGREC = $18610 ; 3 x 32 B: rc, err, mtc0, spin, csr, cer, mtc, mar
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DGREC_SZ = 32
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DGWIN = $18680 ; u32 return of the WINDOWED dma read (want -1)
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DGWERR = $18684 ; u32 SC_ERR after it (want SCE_WINDOW)
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DGLBA = 1000 ; a NON-ZERO LBA throughout: a driver that emits
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; a malformed LBA field still passes LBA 0
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DGBLK = 4 ; 4 x 512 = 2,048 B
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DGDST0 = $20000 ; PIO
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DGDST1 = $24000 ; DMA, bus held
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DGDST2 = $28000 ; DMA, cycle stealing
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org $10000
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start:
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clr.l DGFLAG.l
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; ---- 1. the PIO path, unchanged, as the reference the other two are measured
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; against. It is here so that a DMA failure cannot be confused with a SCSI
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; protocol failure: if this one is wrong, nothing below is about the DMAC.
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bsr scsi_init
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move.l #DGLBA,d3
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moveq #DGBLK,d4
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lea DGDST0,a1
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bsr scsi_read
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lea DGREC,a0
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bsr dg_save
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; ---- 2. the channel, WITH THE BUS HELD
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bsr scsi_init
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move.l #DM_HELD_DCR,DM_DCRV.l
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move.l #DM_HELD_OCR,DM_OCRV.l
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move.l #1,DM_USE.l ; after scsi_init, which clears it
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move.l #DGLBA,d3
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moveq #DGBLK,d4
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lea DGDST1,a1
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bsr scsi_read
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lea DGREC+DGREC_SZ,a0
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bsr dg_save
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; ---- 3. the channel, STEALING CYCLES. Same bytes, same code, two register
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; values different -- which is what makes the comparison a comparison.
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bsr scsi_init
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move.l #DM_STEAL_DCR,DM_DCRV.l
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move.l #DM_STEAL_OCR,DM_OCRV.l
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move.l #1,DM_USE.l
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move.l #DGLBA,d3
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moveq #DGBLK,d4
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lea DGDST2,a1
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bsr scsi_read
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lea DGREC+2*DGREC_SZ,a0
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bsr dg_save
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; ---- 4. and a WINDOWED read through the channel, which must be REFUSED. This
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; is the one test here that is expected to fail, and it has to fail LOUDLY: the
|
||||
; alternative is a channel writing a whole sector into a ring that has room for
|
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; a record, over the top of records the decoder has not finished with.
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bsr scsi_init
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move.l #DM_HELD_DCR,DM_DCRV.l
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move.l #DM_HELD_OCR,DM_OCRV.l
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move.l #1,DM_USE.l
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move.l #300,SC_WSKIP.l ; a record that starts 300 B into a sector
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move.l #1024,SC_WKEEP.l
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move.l #DGLBA,d3
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moveq #DGBLK,d4
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lea DGDST2,a1
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bsr scsi_read_win
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move.l d0,DGWIN.l
|
||||
move.l SC_ERR.l,DGWERR.l
|
||||
|
||||
move.l #1,DGFLAG.l
|
||||
hold: bra.s hold
|
||||
|
||||
; ---- one config's result, copied out of the shared reporting words before the
|
||||
; next run overwrites them. d0 = scsi_read's return; a0 = where it goes.
|
||||
dg_save:
|
||||
move.l d0,(a0)+
|
||||
move.l SC_ERR.l,(a0)+
|
||||
move.l DM_MTC0.l,(a0)+
|
||||
move.l DM_SPIN.l,(a0)+
|
||||
move.l DM_CSRF.l,(a0)+
|
||||
move.l DM_CERF.l,(a0)+
|
||||
move.l DM_MTCF.l,(a0)+
|
||||
move.l DM_MARF.l,(a0)+
|
||||
; and clear them, so a config that never reached the channel reports
|
||||
; zeros of its own rather than the previous config's numbers.
|
||||
clr.l DM_MTC0.l
|
||||
clr.l DM_SPIN.l
|
||||
clr.l DM_CSRF.l
|
||||
clr.l DM_CERF.l
|
||||
clr.l DM_MTCF.l
|
||||
clr.l DM_MARF.l
|
||||
rts
|
||||
|
||||
include "src/player/scsi.i"
|
||||
@@ -125,6 +125,8 @@ SCE_SELTMO = 1 ; the target never answered selection
|
||||
SCE_PHASE = 2 ; the bus went somewhere unexpected
|
||||
SCE_TIMEOUT = 3 ; a poll loop ran out of patience
|
||||
SCE_STATUS = 4 ; the target returned non-zero status
|
||||
SCE_WINDOW = 5 ; a WINDOWED read was asked of the DMAC,
|
||||
; which cannot drop bytes (58.3/P4a)
|
||||
|
||||
SC_ERR = $18200 ; u32 last error
|
||||
SC_STAT = $18204 ; u32 SCSI status byte from the last cmd
|
||||
@@ -237,6 +239,8 @@ sci1: nop
|
||||
move.b #$FF,SC_INTS ; INTS is cleared by writing its bits
|
||||
move.b #0,SC_PCTL
|
||||
clr.l SC_ERR.l
|
||||
clr.l DM_USE.l ; PIO unless a caller asks otherwise,
|
||||
; AFTER this call (src/player/dma.i)
|
||||
clr.l SC_TRN.l
|
||||
move.l #0,SC_TAG.l
|
||||
bsr sc_snap
|
||||
@@ -439,6 +443,26 @@ sip3: move.b SC_DREG,(a1)+
|
||||
; the same limitation sc_in_pio's caller already carries -- and the fix is the
|
||||
; same one: d5 has to become what each phase actually delivered.
|
||||
sc_in_data:
|
||||
; ---- P4a: the DATA IN phase can be handed to the HD63450 instead, and
|
||||
; when it is, the CPU touches none of these bytes. src/player/dma.i.
|
||||
; The window is REFUSED rather than ignored: a channel writes a
|
||||
; contiguous run and cannot be told to drop the first 300 bytes, so a
|
||||
; windowed DMA read would deliver the neighbours' bytes into the ring
|
||||
; and the block loop has no bounds check to catch it (49.2, 58.3).
|
||||
; Refusing it here is what makes "sector-aligned records" a PRECONDITION
|
||||
; the transport states rather than an assumption it carries.
|
||||
tst.l DM_USE.l
|
||||
beq.s .pio
|
||||
tst.l SC_WSKIP.l
|
||||
bne.s .nowin
|
||||
move.l SC_WKEEP.l,d0
|
||||
cmp.l d1,d0
|
||||
bne.s .nowin
|
||||
bra sc_in_dma
|
||||
.nowin: move.l #SCE_WINDOW,SC_ERR.l
|
||||
moveq #-1,d0
|
||||
rts
|
||||
.pio:
|
||||
movem.l d6-d7,-(sp)
|
||||
move.b d2,SC_PCTL
|
||||
move.l d1,d0
|
||||
@@ -657,3 +681,9 @@ scr_phase:
|
||||
move.l #SCE_PHASE,SC_ERR.l
|
||||
moveq #-1,d0
|
||||
bra.s scr_out
|
||||
|
||||
; ---- the DMAC side of the data phase, ROADMAP P4a. Included unconditionally
|
||||
; so that there is ONE transport file: sc_in_data dispatches on DM_USE, which
|
||||
; scsi_init clears, so a front-end that never sets it assembles the same PIO
|
||||
; path FINDINGS 58 measured and executes not one instruction of the following.
|
||||
include "src/player/dma.i"
|
||||
|
||||
Reference in New Issue
Block a user