Put the data phase on the DMAC, and find auto-request is charged by time

ROADMAP P4a. src/player/dma.i programs HD63450 channel 1 and takes the SCSI DATA
IN phase off the CPU; src/player/dmagate.s reads the same 2,048 B at LBA 1000
three ways -- PIO, the channel with the bus held, the channel stealing cycles --
and all three are byte-exact against the host's copy of the volume.

The evidence never reads $EA0015, because 57.3 established that it cannot: with
the DMAC's OWN asserted MAME cannot tell a CPU-driven byte there from a
DMAC-driven one. The discriminator is the CPU's own progress. MTC is sampled by
the INSTRUCTION AFTER the one that starts the channel, and held it reads 0 of
2,048 -- the whole transfer happened between two instructions, because the 68000
did not execute in between -- against the full count and 426 loop trips for the
stealing configuration. Put the stealing registers in the held slot and every
byte still arrives and tools/bench/dma_run.sh goes RED, which is what says the
counter can come out different; 58.3's vacuous "UNDERRUNS: 0/120" is the trap
being avoided. tools/analysis/27_dmac_config.py decodes the four register bytes
out of the player's own source, with the MC68450 field tables now in one copy
(tools/analysis/mc68450.py) shared with 21_iplrom_dmac.py, so the player's
configuration and the IPL ROM's 16..19 clk/B one are the same decoding.

Three bounds on the apparatus, read out of MAME 0.277 rather than inferred: the
CZ-6BS1 has NO request line to the DMAC (its flow control is DTACK), so external
request cannot be run; single address cannot be run either, because only channel
0 has device callbacks; and only burst is modelled as held. Of the four rows of
the W ladder exactly one -- dual address held -- has a code path here, and it is
the one demonstrated. W did not move by one clock, for the third session running.

What outlives the emulator is the currency. Every W in this project is clocks per
DELIVERED byte, which presumes the device asks; an auto-requested channel spends
its share of the bus whether or not a byte is there, so a record costs what it
costs to ARRIVE -- halve the delivery rate and the CPU cost of the same record
doubles. tools/analysis/28_autorequest_cost.py prices it from MC68450 3.8 and
5.2.3.3.2, gating its formulas against Table 5-3's sixteen rows first. At 37,405
B and an explicit 460 KB/s: max rate costs the whole 95.3% of a frame the record
takes to land, and of the GCR's four bus shares only BR=00, 50%, carries the
rate -- 10.61 clk/B, 47.6% of a frame, against 40.4% for the W=9 row and 391.8%
measured for PIO. The GCR is a design lever nothing in this tree had named.

59.4 changes what is left. sc_in_data now REFUSES a windowed read when the data
phase is the channel's (SCE_WINDOW), because a channel writes a contiguous run
and cannot drop the 300 B in front of a record. 117 of 120 records need one, so
sector-aligned records have gone from a preference in ROADMAP's re-encode bundle
to the precondition the transport enforces -- and that bundle is now the only
thing between this tree and M2.

One collision, recorded because the procedure is the finding: DM_USE first sat at
$18300, which is ring.i's XF_SLOT mailbox, and the P4b stage -- untouched by this
work -- went red on a run that never reached its snapshot. check.sh was ALL GREEN
before any of this, which is what made that red unambiguous. ALL GREEN after too,
with one new stage. decode.bin is unchanged at 1,296 B and the same MD5.

Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6

tools/bench/check.sh

@@ -504,6 +504,50 @@ else
   echo "  SKIPPED: no chdman (ships with mame-tools) -- cannot build the volume"
 fi
 
+echo "--- session 27: the DMAC drives the data phase, and holds the bus (FINDINGS 59) ---"
+# ROADMAP P4a, the last item before M2. The two stages above have the CPU moving
+# every byte itself, at the 87.28 clocks per delivered byte FINDINGS 58.2
+# measured -- 391.8% of a 12 fps frame. This one hands the DATA IN phase to the
+# HD63450 and gates on the thing 57.3 said would be hard to show: that the DMAC,
+# and not the CPU, is driving it.
+#
+# IT IS GATED WITHOUT LOOKING AT $EA0015, and that is the design. With the
+# DMAC's OWN asserted -- which it is at idle here -- MAME cannot distinguish a
+# CPU-driven byte at that address from a DMAC-driven one, so watching it proves
+# nothing. What is gated instead is THE CPU'S OWN PROGRESS:
+#   * the same 2,048 B off the disc three ways -- PIO, held, stealing -- all
+#     three byte-exact against the host's copy, so the configuration is being
+#     compared against a delivery that works and not against nothing;
+#   * MTC sampled by the INSTRUCTION AFTER the one that starts the channel: zero
+#     in the held configuration (the whole transfer happened between two
+#     instructions, because the 68000 did not execute in between) and the full
+#     count in the stealing one;
+#   * the CPU's own trip count round its wait loop: 1 against hundreds. A
+#     counter that CANNOT come out different is 58.3's vacuous "UNDERRUNS: 0/120"
+#     again, so the run asserts the contrast and not just the held value;
+#   * the channel's own CSR/CER/MTC/MAR, which must say it moved every byte
+#     without error;
+#   * and a WINDOWED read through the channel REFUSED. 117 of 120 records start
+#     part way into a sector (58.3); a channel writes a contiguous run and cannot
+#     drop the bytes in front of one, so it would write the neighbouring records
+#     into the ring with no bounds check to catch it (49.2). The refusal is what
+#     makes "sector-aligned container" a precondition the transport states.
+#
+# NOT GATED ON RATE, and it cannot be: MAME's DMAC runs on wall-clock attotimes
+# (42.5) and models a held bus by HALTING the CPU rather than by charging it
+# cycles per operand. `W` is untouched. tools/analysis/28_autorequest_cost.py
+# prices what this configuration costs, from the datasheet and an explicit rate.
+# Skipped rather than failed when chdman is absent.
+if command -v chdman > /dev/null; then
+  bash tools/bench/dma_run.sh "$DLX" > tmp/dma_gate.log 2>&1 || {
+    echo "FAIL: the DMAC did not drive the SCSI data phase."
+    tail -16 tmp/dma_gate.log; exit 1; }
+  grep -aE "BYTES OK|MTC one instruction|trips round|REFUSED" tmp/dma_gate.log \
+    | sed 's/^ *//;s/^/  /'
+else
+  echo "  SKIPPED: no chdman (ships with mame-tools) -- cannot build the volume"
+fi
+
 echo "--- session 24: the scene graph, and the gap between branch points (FINDINGS 56) ---"
 # The arcade scene graph is not in this repo and is not redistributable from
 # here. tools/import/scenegraph.py is the ONE file in the tree that knows the