Ask the chip which decoder it is, and find four wrong axes where one was expected
ROADMAP P6a, on the machine. 68000 code programs HD63450 channel 3 with the IPL ROM's own ADPCM bytes -- dual address, 8-bit port, cycle steal, external request -- and feeds the MSM6258 a designed 1,678-nibble stream at the chip's own pace: 839 B in 0.1074 s = 7,811.4 B/s against the format's 7,812.5, CER=$00. That transport is P6b's, not scaffolding. Sixteen candidate decoder models, three capture decimations and a searched prologue are fitted to MAME's capture. Exactly one reproduces it sample-exact over all 1,678 samples, and every axis carries a negative control: flip it alone and the closest survivor disagrees on 826, 1,504, 156 and 1,522 samples. The chip runs 'terms', takes the LOW nibble of a byte first, clamps the accumulator at 10 bits and starts it at -2. tools/encoder/adpcm.py defaulted to the opposite of all four, and 65.2 named the wrong axis as the risk: the delta formula is worth -2.88 dB and the NIBBLE ORDER is worth -25.74 dB. 65.1's "high first, measured" was a measurement of ffmpeg, i.e. of the VOX file convention, which is a different question from what a chip does with a byte in its data register. The 10-bit clamp is free on the Singe window and only because that window peaks at 435 of 511 -- 1.4 dB of headroom on a -13.4 dBFS passage, 12.1 dB below where the encoder was clamping, and inside the recursion. So the audio level is an open choice again, downward, and the loudest passage on the disc is unmeasured. Session 33's silence had two ordinary causes: the PPI's port C is an input until control word $92 says otherwise, and $01 is COMMAND_STOP. And a rig fact worth the space: the 8 MHz ADPCM clock is CT1 in the YM2151's $1B, delivered on the sound system's schedule rather than at the store, so a transfer started in the same breath as the setup plays its first ~17 ms at the old clock and no model fits a stream that changed rate part way through. Name the layer: this is MAME 0.277's okim6258 device model measured end to end through the machine's real transport. It settles the rig and not the silicon. Also struck: 64.4's "no MAME source tree is on this machine" -- there is none on disk, but the machine has network and the upstream tag fetches. check.sh ALL GREEN before (tmp/check_s34_start.log) and after (tmp/check_s34_end.log), with one new stage. Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6
This commit is contained in:
prosolis
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; ---------------------------------------------------------------------------
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; adpcm.i -- the MSM6258V, driven the way the machine's own ROM drives it.
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; ROADMAP P6a, and it is P6b's transport arriving early rather than scaffolding.
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;
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; NOTHING HERE IS INVENTED. Every register value below is one that
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; tools/analysis/21_iplrom_dmac.py decodes OUT OF THE IPL ROM's own bytes, at
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; the addresses it prints: channel 3's DCR/SCR/MFC/CPR/DFC/DAR at $FF0C2E and
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; the per-transfer OCR = $32 plus command $02 at $FF9A82. That is the one
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; ADPCM path on this board that is known-correct because Sharp wrote it.
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;
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; WHY THIS FILE EXISTS AT ALL. Session 33 fed the chip from Lua and got
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; silence, swept control 0..3 against port C 0..15, and stopped rather than
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; guess (65.5). Two of the reasons are visible from here and neither is a
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; register semantic anybody had to guess:
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;
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; * THE PPI'S PORT C IS NOT AN OUTPUT UNTIL IT IS TOLD TO BE. The ADPCM pan
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; and the sample-rate divider are port C bits, and an i8255 in its reset
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; state has every port an INPUT -- so a write to $E9A005 changes a latch
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; nobody is reading and the pan never leaves wherever it was. Control word
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; $92 (mode 0, A and B input, both halves of C OUTPUT) is what makes the
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; other write mean anything.
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; * AND FEEDING IT SLOWLY IS NOT FEEDING IT. The chip has no FIFO and no
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; starvation state: it consumes a nibble every sample period out of whatever
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; its data register last held, forever. A byte per host frame is not a
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; quiet chip, it is the same two nibbles 130 times, which saturates in six
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; samples. The feed has to be paced by the chip, which is what channel 3
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; and its request line are FOR.
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;
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; THE CLOCK IS TWO WRITES AND THEY ARE IN DIFFERENT DEVICES. 15,625 Hz is
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; 8 MHz / 512: the 8 MHz comes from CT1 in the YM2151's port register $1B, and
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; the /512 from port C bits 3,2 = 10. Neither is readable, so the rate is
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; verified from the OTHER end -- the capture's own sample count.
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AD_CTRLR = $E92001 ; W: command R: status (bit7 = NOT playing)
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AD_DATAR = $E92003 ; W: the byte the chip takes two nibbles from
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AD_PLAY = $02 ; COMMAND_PLAY -- session 33's probes wrote $01,
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AD_STOP = $01 ; which is COMMAND_STOP
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PPI_PC = $E9A005
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PPI_CTL = $E9A007
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PPI_COUT = $92 ; mode 0, A/B input, BOTH halves of C output
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PPI_RATE = $08 ; pan 00 = both, rate 10 = /512 = 15,625 Hz
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YM_ADDR = $E90001
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YM_DATA = $E90003
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YM_CT = $1B ; CT1 in bit 1: 0 = ADPCM master clock 8 MHz
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AD_DMAC = $E840C0 ; HD63450 channel 3 -- the ADPCM channel, and
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A3_CSR = AD_DMAC+$00 ; the one the ROM points at $E92003
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A3_CER = AD_DMAC+$01
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A3_DCR = AD_DMAC+$04
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A3_OCR = AD_DMAC+$05
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A3_SCR = AD_DMAC+$06
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A3_CCR = AD_DMAC+$07
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A3_MTC = AD_DMAC+$0A
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A3_MAR = AD_DMAC+$0C
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A3_DAR = AD_DMAC+$14
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A3_MFC = AD_DMAC+$29
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A3_CPR = AD_DMAC+$2D
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A3_DFC = AD_DMAC+$31
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A3_DCRV = $80 ; XRM 10 cycle steal w/o hold, DTYP 00 dual
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; address, DPS 0 8-bit port (IPL $FF0C2E)
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A3_OCRV = $32 ; DIR memory->device, SIZE 11 byte unpacked,
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; CHAIN 00, REQG 10 EXTERNAL REQUEST (IPL
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; $FF9A82). External request is what makes the
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; chip the pacemaker: one byte per #DRQ3, and
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; #DRQ3 ticks at half the sample rate.
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A3_SCRV = $04 ; MAC 01 memory increment, DAC 00 -- the device
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; address is a REGISTER and must not walk
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A3_CCRST = $80
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; --------------------------------------------------------------- ad_setup
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; The clock and the pan. No arguments, no result; trashes d0.
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ad_setup:
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move.b #YM_CT,YM_ADDR
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moveq #60,d0 ; the YM2151 wants settling between the
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.ymw: subq.l #1,d0 ; address write and the data write
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bne.s .ymw
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move.b #$00,YM_DATA ; CT1 = 0 -> ADPCM master clock 8 MHz
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move.b #PPI_COUT,PPI_CTL ; ...and NOW port C drives something
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move.b #PPI_RATE,PPI_PC ; pan both, /512
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rts
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; ----------------------------------------------------------------- ad_arm
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; Arm channel 3 to feed (a1) for d1 bytes and start it. Trashes d0.
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; The channel is started BEFORE the chip is told to play (see ad_play), so that
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; byte 0 is already in the data register when the accumulator is reset.
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ad_arm:
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move.b #$FF,A3_CSR ; CSR is write-one-to-clear: a stale COC
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; would pass the wait loop instantly
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move.b #A3_DCRV,A3_DCR
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move.b #A3_SCRV,A3_SCR
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move.b #$05,A3_MFC
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move.b #$05,A3_DFC
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move.b #$01,A3_CPR ; the ROM's own priority: ADPCM outranks
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; the disk at the arbiter (52.5 item 5)
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move.l #AD_DATAR,A3_DAR
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move.b #A3_OCRV,A3_OCR
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move.l a1,A3_MAR
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move.w d1,A3_MTC
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move.b #A3_CCRST,A3_CCR
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rts
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ad_play:
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move.b #AD_PLAY,AD_CTRLR
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rts
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ad_halt:
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move.b #AD_STOP,AD_CTRLR
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rts
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@@ -0,0 +1,112 @@
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; Front-end for the ADPCM transport (ROADMAP P6a), for the rig.
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;
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; It plays ONE buffer of nibbles the host pushed into RAM and reports what the
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; channel did. What is being measured is not this code -- it is the CHIP: which
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; delta formula, which nibble of a byte first, where the accumulator clamps, and
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; what it starts at. tools/bench/verify_adpcm_chip.py reads all four out of
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; MAME's own -wavwrite capture.
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;
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; THE ONE THING THIS FILE HAS TO GET RIGHT is the order of the two starts. The
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; chip resets its accumulator, its step index AND its nibble select when it is
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; told to PLAY, and it begins consuming immediately out of whatever its data
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; register holds. So the channel goes first and the CPU waits for MTC to move
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; -- proof that a byte has actually been taken -- before the PLAY. The stream
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; still has a prologue of unknown length, because the gap between PLAY and the
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; NEXT #DRQ3 is not ours to set; the prologue is 16 zero nibbles for exactly
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; that reason and the verifier reads its length off the capture.
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include "src/player/geom.i"
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AD_FLAG = $18600 ; u32 0 idle, 1 armed, 2 playing, $FF done, $EE error
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AD_BUF = $18604 ; u32 where the nibble bytes are
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AD_LEN = $18608 ; u32 how many bytes
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AD_MTC0 = $1860C ; u32 MTC at the instant PLAY was written
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AD_CSRF = $18610 ; u32 CSR at completion
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AD_CERF = $18614 ; u32 CER with it
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AD_MTCF = $18618 ; u32 MTC with it
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AD_MARF = $1861C ; u32 MAR with it -- where the channel stopped
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AD_SPIN = $18620 ; u32 trips round the wait loop
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AD_STAT = $18624 ; u32 the chip's own status byte while playing
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AD_PATIENCE = 60000000
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AD_SETTLE = 60000 ; ~100 ms at 10 MHz, 18 clocks a trip ; the wait is bounded like every other
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org $10000
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start:
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bsr ad_setup
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; ---- SETTLE, and it is not superstition. The 8 MHz ADPCM clock is
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; CT1 in the YM2151's port register, and this machine delivers that
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; write to the ADPCM chip on the SOUND system's own schedule rather
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; than at the instant of the store -- so a transfer started in the same
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; breath as ad_setup plays its first ~17 ms at the PREVIOUS clock. The
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; symptom is exact: the capture's first 130-odd samples come out in
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; identical PAIRS, because the chip is clocking half as fast as the
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; capture, and every model then fails to fit a stream that changed rate
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; part way through. ~100 ms of nothing costs the gate nothing and a
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; player sets its clock once at boot.
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move.l #AD_SETTLE,d0
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.settle:subq.l #1,d0
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bne.s .settle
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movea.l AD_BUF.l,a1
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move.l AD_LEN.l,d1
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bsr ad_arm
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move.l #1,AD_FLAG.l
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; ---- wait for the channel to actually take byte 0. Not a delay loop:
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; the condition is MTC having moved, which is the channel's own account.
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move.l #AD_PATIENCE,d3
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.first: move.w A3_MTC,d0
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andi.l #$FFFF,d0
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cmp.l AD_LEN.l,d0
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bne.s .go
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subq.l #1,d3
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bne.s .first
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bra bad
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.go: move.l d0,AD_MTC0.l
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bsr ad_play
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move.l #2,AD_FLAG.l
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moveq #0,d0
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move.b AD_CTRLR,d0 ; bit 7 clear = the chip says it is playing
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move.l d0,AD_STAT.l
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clr.l AD_SPIN.l
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move.l #AD_PATIENCE,d3
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.wait: addq.l #1,AD_SPIN.l
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move.b A3_CSR,d4
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btst #4,d4 ; ERR -- CER says which
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bne.s bad
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btst #7,d4 ; COC
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bne.s .fin
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subq.l #1,d3
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bne.s .wait
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bra.s bad
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.fin: bsr report
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; The chip is left PLAYING deliberately: it goes on replaying the last
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; byte it was given, which the verifier ignores. Stopping here would
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; put a silence in the capture at a point the host would then have to
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; find, and the capture already has a length it knows.
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move.l #$FF,AD_FLAG.l
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hold: bra.s hold
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bad: bsr report
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move.l #$EE,AD_FLAG.l
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bra.s hold
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report:
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moveq #0,d0
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move.b A3_CSR,d0
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move.l d0,AD_CSRF.l
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moveq #0,d0
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move.b A3_CER,d0
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move.l d0,AD_CERF.l
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move.w A3_MTC,d0
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andi.l #$FFFF,d0
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move.l d0,AD_MTCF.l
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move.l A3_MAR,d0
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move.l d0,AD_MARF.l
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rts
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include "src/player/adpcm.i"
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