"""MC68450 / HD63450 register field layouts, in ONE copy.

Read by tools/analysis/21_iplrom_dmac.py, which decodes what the X68000's IPL
ROM programs into the DMAC, and by tools/analysis/27_dmac_config.py, which
decodes what src/player/dma.i programs into it.  The two exist to be COMPARED
-- the ROM's own disk channel costs 16..19 clocks a byte (FINDINGS 52.5) and
the player's job is to be cheaper -- and a comparison between two decodings
that used two copies of these tables would not be one.  This tree has already
paid twice for a transform with two copies of itself (FINDINGS 49.7.5).

SOURCED: MC68450 Direct Memory Access Controller, Motorola, Jul 1989
(bitsavers) -- the same document FINDINGS 39 cites for the transfer timings in
tools/analysis/buscost.py.
"""
# --- MC68450 register map, by offset inside a channel's 0x40 block ----------
REG = {0x00: "CSR", 0x01: "CER", 0x04: "DCR", 0x05: "OCR", 0x06: "SCR",
       0x07: "CCR", 0x0A: "MTC", 0x0C: "MAR", 0x14: "DAR", 0x1A: "BTC",
       0x1C: "BAR", 0x25: "NIV", 0x27: "EIV", 0x29: "MFC", 0x2D: "CPR",
       0x31: "DFC", 0x39: "BFC"}

XRM  = {0: "burst",
        1: "UNDEFINED",
        2: "cycle steal WITHOUT hold  (bus released between operands)",
        3: "cycle steal with hold"}
DTYP = {0: "68000-compatible, EXPLICITLY addressed  -> DUAL ADDRESS",
        1: "6800-compatible, EXPLICITLY addressed   -> DUAL ADDRESS",
        2: "device with ACK, implicitly addressed   -> SINGLE ADDRESS",
        3: "device with ACK and RDY, implicit       -> SINGLE ADDRESS"}
DPS  = {0: "8-bit port", 1: "16-bit port"}
PCL  = {0: "status input", 1: "status input with interrupt",
        2: "start pulse", 3: "abort input"}
SIZE = {0: "byte", 1: "word", 2: "long word", 3: "byte, unpacked"}
CHAIN= {0: "none", 1: "UNDEFINED", 2: "array", 3: "linked array"}
REQG = {0: "auto-request at limited rate", 1: "auto-request at max rate",
        2: "EXTERNAL request  (one operand per device request)",
        3: "auto-request first operand, external thereafter"}


def dcr(v):
    return [f"XRM  = {v>>6&3:02b}  {XRM[v>>6&3]}",
            f"DTYP = {v>>4&3:02b}  {DTYP[v>>4&3]}",
            f"DPS  = {v>>3&1:b}   {DPS[v>>3&1]}",
            f"PCL  = {v&3:02b}  {PCL[v&3]}"]


def ocr(v):
    return [f"DIR  = {v>>7&1:b}   " +
            ("device -> memory (read)" if v & 0x80 else "memory -> device (write)"),
            f"SIZE = {v>>4&3:02b}  {SIZE[v>>4&3]}",
            f"CHAIN= {v>>2&3:02b}  {CHAIN[v>>2&3]}",
            f"REQG = {v&3:02b}  {REQG[v&3]}"]


def scr(v):
    m = {0: "no count", 1: "increment", 2: "decrement", 3: "UNDEFINED"}
    return [f"MAC  = {v>>2&3:02b}  memory address {m[v>>2&3]}",
            f"DAC  = {v&3:02b}  device address {m[v&3]}"]