prosolis
c520a89e14
blit.s gains v7 -- v6's 24-pixel movem chain plus a second chain whose unit is
one `move.l (a0)+,(a2)+`. Measured over 13 span lengths by span.sh, every config
pixel-exact:
cycles = 66.0 per span + 9.143 per COARSE pixel + 9.978 per FINE pixel
fitting all 13 to within 0.2%. v5 and v6 re-measure to FINDINGS 30 exactly, so
the harness has not drifted underneath the new variant.
Rescored against the same scsi window and the same additive model, v7 takes
84/120 frames over budget to 18/120 -- exactly what FINDINGS 39.4 derived, and
that agreement is two cancelling errors: the derivation's 2-register movem tail
is 29% too dear per pixel, and its "nothing per span" for the second chain entry
is 22.3 clocks too cheap. The plain post-incrementing move.l is the right tail
instruction, and it makes the padding quantum 2 pixels, which a run of 4x4
blocks pads to exactly zero.
The DMAC stays dropped on a measurement now rather than an argument: v7 takes
back 37 of the 43 frames the array chain would, with no reserved channel and no
timing neither emulator here can verify. Break-even against all-V1 moves from
L=4 blocks to L=2.
The fine displacement is carried mid-stream rather than in the span record, so
the decoder holds nothing across the copy and keeps all 12 payload registers --
which is the whole reason the coarse unit is 24 pixels.
span.sh is now -seconds_to_run 200 (30 s wall, 36 configs) and takes its
expected snapshot count from the generated metadata instead of a literal 23.
Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6
164 lines
7.5 KiB
Python
164 lines
7.5 KiB
Python
"""Bus-cycle cost of src/player/decode.s and of tools/bench/blit.s's v6 spans.
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A 68000 bus cycle is 4 clocks (S0-S7) with no wait states, and the 68000
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prefetches every instruction word over the same bus. So a block's bus cost is
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`instruction words + data accesses`, a long access counting twice on the 16-bit
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bus and `movem.l` of N registers counting 2N.
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The per-path word counts are read off tools/bench/decode.lst and
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tools/bench/blit.s. tools/analysis/15_bus_occupancy.py checks the DATA half of
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this table against tools/bench/c68k/c68k_bench, which counts every bus callback
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the C68K core makes: they agree to 0.04%. The prefetch half cannot be measured
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from either emulator -- MAME does not expose a fetch count and C68K reads
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opcodes through a host pointer with no callback -- so it rests on that check.
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"""
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BUS_CLK = 4
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# --- decode.s, per block ---------------------------------------------------
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# dispatch move.b (a1),d0 / lsr.b / and.w #3 / beq .sk 6w, 1 read
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# + subq / beq .v1 -> 8w
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# + subq / bne .rw -> 10w
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# V4 body $10090..$100E2 = 82 B = 41w; 4 x (1 byte read
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# + movem.l 2 = 4 reads + 2 move.l = 4 writes) = 36
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# V1 body $100E2..$10106 = 36 B = 18w; 1 byte read
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# + movem.l 8 = 16 reads + 4 x movem.l 2 = 16 wr = 33
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# RAW body $10106..$10164 = 94 B = 47w; 8 x (2 byte reads
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# + 1 move.l = 2 writes) = 32
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BODY = {0: (0, 0), 1: (18, 33), 2: (41, 36), 3: (47, 32)}
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DISPATCH = {0: 6, 1: 8, 2: 10, 3: 10}
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SK_TAIL = 1 # addq.l #8,a4
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GROUP_HEAD = 3 # tst.b (a1) + beq allskip
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GROUP_TAIL = 4 # addq.l #1,a1 / cmpa.l a5,a4 / bne byteloop
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ALLSKIP = 9 # the whole four-block fast path, tst.b included
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ROW_HEAD, ROW_TAIL = 3, 7
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# --- blit.s v6 spans -------------------------------------------------------
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# One chain unit moves 12 registers = 48 B = 24 pixels:
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# movem.l (a0)+,12 = 2w instr + 24 word reads = 26
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# movem.l 12,(a2) = 2w instr + 24 word writes = 26
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# lea 48(a2),a2 = 2w instr = 2
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# Per span: move.l (a0)+,a2 (1w + 2 reads) + move.w (a0)+,d0 (1w + 1 read)
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# + jmp v6ch(pc,d0.w) (2w) + dbra (2w) = 9
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V6_UNIT_PX = 24
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V6_UNIT_BUS = 54
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V6_SPAN_BUS = 9
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V6_SPAN_CYC = 43.7 # MEASURED, FINDINGS 30
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V6_PX_CYC = 9.152 # MEASURED, FINDINGS 30
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# --- a DMAC array-chaining span -------------------------------------------
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# SOURCED, MC68450 Direct Memory Access Controller, Motorola, Jul 1989
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# (bitsavers). These replace session-10's first pass, which guessed 2 bus
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# cycles a pixel from bus arithmetic and was 12% optimistic.
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#
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# Fig 4-25 sheet 4, DUAL ADDRESS / OPERAND SIZE IS WORD / DEVICE SIZE IS
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# 16-BITS, D->M or M->D: {WORD READ, WORD WRITE} = 9 CLOCKS.
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# Confirmed by the long-operand row: two of each = 18 clocks.
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# Fig 4-25 note 2: reads are 4 clocks and WRITES ARE 5. That extra clock on
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# every write is the whole story -- it is why the DMAC does not beat a 68000
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# movem chain, which writes in 4.
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DMA_PX_CLK = 9
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# Fig 4-25 sheet 1, SEQUENTIAL ARRAY CHAINING: 36 CLOCKS per entry (three
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# word reads to fetch the 6-byte entry, plus reload).
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DMA_CHAIN_CLK = 36
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# Sect 4.5.2.1 front-end overhead 5 clocks best case, 8 worst; 4.5.2.2
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# back-end 2 clocks best. Once per period of bus ownership, not per span.
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DMA_FRONT_CLK, DMA_BACK_CLK = 5, 2
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# Fig 4-25 sheet 3, SINGLE ADDRESS: W/B READ 4 clocks, W/B WRITE 5 clocks.
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# A device->memory disk transfer is one memory WRITE = 5 clocks if the DMAC
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# holds the bus, or 5 + front + back = 12 if it arbitrates per word.
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# FINDINGS 5's long-standing 8 clk/word ESTIMATE sits inside that range.
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DMA_DISK_CLK_WORD_HELD, DMA_DISK_CLK_WORD_ARB = 5, 12
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# The 68000 cannot execute while another master owns the bus: no cache, and a
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# two-word prefetch queue that empties immediately. So DMA time is ADDITIVE to
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# CPU time, not overlapped -- which is what FINDINGS 35's flat debit assumed
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# and session 10's first pass wrongly "refined".
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DMA_OVERLAPS = False
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def pad24(npix):
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return -(-npix // V6_UNIT_PX) * V6_UNIT_PX
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def block_bus(mode_map, spanned=None):
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"""(instruction words, data accesses) for one frame's CPU block decode.
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`spanned` is a boolean array the same shape as mode_map marking blocks a
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span will paint instead; those blocks still cost their dispatch, because
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the mode map is walked either way, but not their body."""
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nby, nbx = mode_map.shape
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pref = nby * (ROW_HEAD + ROW_TAIL)
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data = 0
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for by in range(nby):
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row = mode_map[by]
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sp = spanned[by] if spanned is not None else None
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for gi in range(0, nbx, 4):
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g = row[gi:gi + 4]
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if (g == 0).all():
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pref += ALLSKIP
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data += 1
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continue
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pref += GROUP_HEAD + GROUP_TAIL - 1 # BLOCK 0 has no lsr.b
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data += 1
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for k, b in enumerate(g):
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b = int(b)
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if sp is not None and sp[gi + k]:
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b = 0 # the span paints it
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pw, pd = BODY[b]
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pref += DISPATCH[b] + pw + SK_TAIL
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data += 1 + pd
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return pref, data
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# --- v7: v6 with a finer tail (MEASURED, session 11, FINDINGS 40) ----------
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# v6 pads every span up to 24 pixels because its unrolled chain is built from
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# 12-register movem units, and FINDINGS 39.3 attributed 86% of the DMAC array
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# chain's advantage over v6 to exactly that padding. v7 keeps the coarse chain
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# and appends a second chain whose unit is one `move.l (a0)+,(a2)+` -- 2 pixels,
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# so the quantum is 2 and a run of 4x4 blocks pads to NOTHING.
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#
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# Session 10 proposed a 2-REGISTER MOVEM tail (4 pixels, derived at 56 clocks)
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# and that would have been the wrong instruction: movem.l (a0)+,d0-d1 plus
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# movem.l d0-d1,(a2) plus the lea is 14 bus cycles for 4 pixels, where two plain
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# move.l are 10. The plainest instruction on the machine wins the tail.
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#
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# The second entry point needs a second dispatch, and the fine displacement is
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# carried MID-STREAM (after the coarse pixels, before the fine ones) rather than
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# in the span record, so the decoder holds nothing extra across the copy and
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# keeps all 12 payload registers. Costed as 2 more bytes per span.
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#
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# MEASURED by tools/bench/span.sh (blit.s v7, 13 span lengths, every config
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# pixel-exact): cycles = 66.0/span + 9.143/coarse pixel + 9.978/fine pixel,
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# fitting all 13 to within 0.2%.
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V7_SPAN_CYC = 66.0 # MEASURED, FINDINGS 40
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V7_CPX_CYC = 9.143 # MEASURED, FINDINGS 40 (24-pixel coarse unit)
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V7_FPX_CYC = 9.978 # MEASURED, FINDINGS 40 (2-pixel fine unit)
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V7_FINE_PX = 2
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# Bus: per span v6's 9 plus a second {move.w (a0)+,d0 ; jmp} = 2 + 2.
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# Per fine unit: move.l (a0)+,(a2)+ = 1 instruction word + 2 reads + 2 writes.
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V7_SPAN_BUS = 13
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V7_FINE_BUS = 5
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V7_SPAN_HDR = 8 # {u32 address, u16 coarse disp} + u16 fine disp
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def pad2(npix):
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return -(-npix // V7_FINE_PX) * V7_FINE_PX
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def v7_span(npix):
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"""(pixels carried, CPU clocks) for a v7 span of npix pixels."""
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k, r = divmod(pad2(npix), V6_UNIT_PX)
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return (k * V6_UNIT_PX + r,
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V7_SPAN_CYC + k * V6_UNIT_PX * V7_CPX_CYC + r * V7_FPX_CYC)
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def v7_span_bus(npix):
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"""Bus CYCLES a v7 span occupies -- instruction words plus data accesses."""
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k, r = divmod(pad2(npix), V6_UNIT_PX)
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return V7_SPAN_BUS + k * V6_UNIT_BUS + (r // V7_FINE_PX) * V7_FINE_BUS
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def v6_span_bus(npix):
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k = pad24(npix) // V6_UNIT_PX
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return V6_SPAN_BUS + k * V6_UNIT_BUS
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