prosolis
c5ca56330e
Three things, and the last one reversed itself when the datasheet arrived.
A SECOND EMULATOR. tools/bench/c68k/ links px68k's C68K core into a headless
harness -- no SDL, no ROMs, no emulated machine, because the decoder touches
nothing but RAM, the control block and GVRAM. decode.s is now pixel-exact under
two independent CPU cores, and cycle-table error against MAME is bounded at
3.3%, running against us. MAME 0.277's M68000 turns out to be the MICROCODE
core, not Musashi (m68000.lst + m68000gen.py), so this is two structurally
different timing models agreeing rather than two tables. FINDINGS 28.8's "V4
costs more than RAW" reproduces independently. FINDINGS 37.
THE BUS. Nothing since FINDINGS 24 had counted the 68000's local memory bus --
one 4-clock cycle at a time, carrying instruction prefetch as well as data. The
decoder occupies 86.7% of it and PREFETCH IS 62% OF THAT TRAFFIC, so a data-only
count understates occupancy by 2x. Two sources check each other: c68k_bench
counts every bus callback exactly, and a static walk of decode.lst supplies the
prefetch no emulator here can report. The walk reproduces the measured data half
to 0.04%, which is what licenses its prefetch half, and 15_bus_occupancy.py is a
gate rather than a report because every bus figure depends on that check.
FINDINGS 38.
THE DMAC CHAIN LOSES. FINDINGS 29.6 named it the one uncosted lever. Costed from
bus arithmetic -- a read cycle plus a write cycle, 8 clocks a pixel -- it scored
1/120 frames over budget against the v6 span's 10/120 and looked decisive. Then
the MC68450 manual (Motorola Jul 1989, now at ~/src/mc68450.pdf): Fig 4-25 sheet
4 puts a dual-address word between two 16-bit ports at 9 CLOCKS, because note 2
gives the DMAC 4-clock reads and 5-clock WRITES. The 68000 writes in 4.
DMAC 9.000 clocks/pixel datasheet
v6 9.152 clocks/pixel measured, FINDINGS 30
1.7%. Scored additively, 86% of what remains of the DMAC's advantage is v6's
24-pixel padding quantum -- a property of its unrolled movem chain, fixable in
software with a finer tail chain, worth 55/120 -> 18/120 against the DMAC's
12/120. Recommendation: fix the quantum, drop the DMAC. Six frames does not buy
a reserved channel, a two-region container layout and a timing dependency
neither emulator here can verify. The container is identical either way -- v6's
record and an HD63450 chaining entry are both 6 bytes, so the chain array IS the
span table -- so nothing is foreclosed. FINDINGS 39.
TWO CORRECTIONS TO MY OWN WORK IN THE SAME SESSION:
- I argued FINDINGS 35's flat CPU debit for the disk was too pessimistic and
rescored the window at 53/120 with max(CPU, bus). Wrong. A 68000 has no cache
and a two-word prefetch queue, so it stalls the moment another master takes
the bus, and the MC68450 hands the bus over in SLABS under limited-rate
auto-request rather than interleaving per operand. DMA is additive. 84/120
stands and 14_dmac_chain.py reproduces it exactly. What 86.7% occupancy really
says is that there is almost no room to overlap anything. FINDINGS 38.3.
- The first DMAC costing was derived where a primary source existed. Both wrong
answers were confident and both were caught by reading the manual.
Also landed:
- FINDINGS 5's 8 clocks/word for the SCSI DMA, STATUS's own "most load-bearing
unmeasured number", is now bracketed by the datasheet: 5 clk/word with the bus
held, ~12 if the DMAC arbitrates per word. 8 is a supported midpoint, and
which end applies is a player design decision worth 7 clocks a word on a
480 KB/s stream. FINDINGS 39.7.
- check.sh gains two gates: the C68K pixel-exact decode (seconds, no MAME) and
the bus-model self-check. Both skip cleanly without a px68k checkout.
- spanned blocks are now charged their mode-map dispatch, which FINDINGS 30.7
flagged as uncounted in 12_span_tradeoff.py.
- MAME timed runs must be budgeted by WALL CLOCK, not -seconds_to_run: this box
runs x68000 at ~0.033x realtime and two runs were killed by their own timeout.
That is why the all-RAW cell in 37.3 is empty. The C68K harness does the same
work in seconds because it emulates a CPU and not a machine.
Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6
215 lines
9.9 KiB
Python
215 lines
9.9 KiB
Python
#!/usr/bin/env python3
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"""Would letting the HD63450 paint the spans beat letting the 68000 do it?
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python3 tools/analysis/14_dmac_chain.py [container.dlx] [--bus 488]
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[--dma-px-bus 2] [--disk-bus-byte 1]
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FINDINGS 29.6 called this the one lever that could move the CPU budget without
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spending a byte, and left it uncosted. FINDINGS 30 measured the alternative --
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the 68000 painting spans itself, 43.7 cycles per span + 9.152 per pixel. This
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prices the two against each other, and the answer turns on a resource neither
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section costed: the 68000's own LOCAL BUS.
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FINDINGS 29's "the bus has 4x the headroom the CPU has" is about the SCSI pipe,
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110 KB/s of 488. That is a different bus. The 68000's memory bus runs one 4-clock
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cycle at a time and carries instruction prefetch as well as data, and
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tools/analysis/15_bus_occupancy.py measures the decoder using 86.7% of it.
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THE TWO DESIGNS ARE THE SAME CONTAINER. v6's record is {u32 absolute GVRAM
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address, u16 jump displacement} = 6 bytes; an MC68450/HD63450 array-chaining
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entry is {u32 memory address, u16 transfer count} = 6 bytes. Set the channel to
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dual-address, direction device->memory, Sequence Control counting both addresses
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up: MAR reloads per entry (the GVRAM destination), DAR walks the stream buffer,
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MTC is the span's word count. The chain array IS the span table.
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THE DMAC CONSTANTS ARE NOW SOURCED, and they killed the first answer. From the
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MC68450 manual (Motorola, Jul 1989, bitsavers), Fig 4-25 sheet 4: a dual-address
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WORD operand between two 16-bit ports is **9 clocks**, because note 2 gives the
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DMAC 4-clock reads and **5-clock writes**. The 68000 writes in 4. So:
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DMAC 9.000 clocks/pixel (datasheet)
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v6 9.152 clocks/pixel (measured, FINDINGS 30)
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A 1.7% difference. Session 10's first pass guessed 2 bus cycles = 8 clocks from
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bus arithmetic and was 12% optimistic; the extra clock on every DMAC write is
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the whole story. Per span, sequential array chaining costs 36 clocks (Fig 4-25
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sheet 1) against v6's measured 43.7 -- the DMAC's one real edge, and it is small.
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AND DMA DOES NOT OVERLAP. The 68000 has no cache and a two-word prefetch queue,
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so it stalls as soon as another master takes the bus. Frame time is therefore
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CPU + DMA, additive. Session 10's first pass used max(CPU, bus) and got 53/120
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where the additive model gives 84/120; FINDINGS 35's flat debit was right.
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So the only material difference left is v6's 24-pixel padding quantum -- and
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that is a property of v6's unrolled chain, not of the CPU. The `v6 fine tail`
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column prices fixing it in software instead.
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"""
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import sys, os, argparse
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sys.path.insert(0, "tools/encoder")
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sys.path.insert(0, "tools/analysis")
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import numpy as np
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from dlx import DLX
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import buscost as B
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FRAME_CYC = 833333.0
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AUDIO_KBPS = 7.8
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C_V1, C_V4, C_RAW = 299.9, 448.2, 400.4 # FINDINGS 28.2 (MEASURED)
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C_SKIP_CLUSTERED, C_SKIP_MIXED = 13.25, 45.0
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SPAN_BYTES_PX, SPAN_HDR = 2, 6
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ap = argparse.ArgumentParser()
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ap.add_argument("container", nargs="?", default="tmp/rc_fr_singe_scsi_cpufit.dlx")
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ap.add_argument("--bus", type=float, default=488.0, help="SCSI pipe, KB/s")
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ap.add_argument("--fps", type=float, default=12.0)
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ap.add_argument("--dma-px-clk", type=float, default=B.DMA_PX_CLK,
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help="clocks the DMAC spends per pixel, dual-address word "
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"between two 16-bit ports. 9 is the DATASHEET figure "
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"(MC68450 Fig 4-25 sheet 4).")
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ap.add_argument("--disk-clk-word", type=float, default=8.0,
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help="clocks the SCSI DMA steals per word. The datasheet "
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"brackets it at 5 (DMAC holds the bus) to 12 (arbitrates "
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"per word); FINDINGS 5's estimate of 8 is the midpoint.")
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a = ap.parse_args()
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if not os.path.exists(a.container):
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sys.exit(f"missing {a.container}")
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BYTE_BUD = (a.bus - AUDIO_KBPS) * 1024 / a.fps
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BUS_SLOTS = FRAME_CYC / B.BUS_CLK
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d = DLX(a.container)
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BLK_C = {1: C_V1, 2: C_V4, 3: C_RAW}
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BLK_B = {1: 1, 2: 4, 3: 16}
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def runs(m, by):
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dirty = m[by] != 0
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i = 0
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while i < d.nbx:
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if not dirty[i]:
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i += 1; continue
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j = i
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while j < d.nbx and dirty[j]:
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j += 1
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yield i, j
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i = j
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def span_cost(design, L):
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"""(pixels carried, clocks charged to the frame) for a run of L blocks,
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as 4 rows of 4L pixels. Every design is charged additively: the 68000
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cannot execute while the DMAC owns the bus."""
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if design == "v6":
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px = B.pad24(4 * L)
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return 4 * px, 4 * (B.V6_SPAN_CYC + px * B.V6_PX_CYC)
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if design == "v6fine":
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px, c = B.v6_fine(4 * L)
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return 4 * px, 4 * c
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px = 4 * L
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return 4 * px, 4 * (B.DMA_CHAIN_CLK + px * a.dma_px_clk)
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def score(design):
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"""Greedy, as 12_span_tradeoff.py: buy the best clocks-saved per byte spent
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until the frame's byte budget is gone. Unlike 12, a spanned block still pays
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its mode-map dispatch, which FINDINGS 30.7 flagged as uncounted."""
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out = []
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for f in range(d.nframes):
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m = d.modes(f).reshape(d.nby, d.nbx)
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byt = d.mode_bytes + sum(BLK_B.get(int(x), 0) for x in m.ravel())
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spanned = np.zeros_like(m, bool)
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span_clk = 0.0
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cand = []
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if design != "none":
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for by in range(d.nby):
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for i, j in runs(m, by):
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L = j - i
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cur_c = sum(BLK_C[int(b)] for b in m[by][i:j])
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cur_b = sum(BLK_B[int(b)] for b in m[by][i:j])
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px, sc = span_cost(design, L)
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sc += L * C_SKIP_MIXED # the dispatch still happens
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span_b = 4 * SPAN_HDR + px * SPAN_BYTES_PX
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if sc < cur_c:
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cand.append((cur_c - sc, span_b - cur_b, by, i, j, sc, L))
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cand.sort(key=lambda s: -(s[0] / max(s[1], 1)))
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for dc, db, by, i, j, sc, L in cand:
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if byt + db <= BYTE_BUD:
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byt += db
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spanned[by][i:j] = True
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span_clk += sc - L * C_SKIP_MIXED
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g = m.copy()
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g[spanned] = 0
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gg = g.reshape(-1, 4)
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allskip = (gg == 0).all(1)
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cpu = allskip.sum() * 4 * C_SKIP_CLUSTERED
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mm = gg[~allskip]
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cpu += (mm == 0).sum() * C_SKIP_MIXED
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for k, c in BLK_C.items():
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cpu += (mm == k).sum() * c
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pref, data = B.block_bus(m, spanned)
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disk = byt / 2.0 * a.disk_clk_word
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# additive: CPU work, then span painting, then the disk stealing the bus
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out.append((cpu + span_clk + disk, (pref + data) * B.BUS_CLK, byt,
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spanned.sum()))
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return np.array(out).T
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DESIGNS = [("today", "none"), ("v6 span", "v6"),
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("v6 fine tail", "v6fine"), ("DMAC chain", "dmac")]
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res = {n: score(k) for n, k in DESIGNS}
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print(f"{a.container}: {d.nframes} frames, {d.nb} blocks, {a.fps:g} fps")
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print(f"SCSI pipe {a.bus:.0f} KB/s -> {BYTE_BUD:,.0f} B/frame; "
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f"68000 bus {BUS_SLOTS:,.0f} cycles/frame; CPU {FRAME_CYC:,.0f} clocks\n")
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print("PER PIXEL AND PER SPAN -- datasheet against measurement")
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print(f" DMAC dual-address word, two 16-bit ports {B.DMA_PX_CLK:.3f} clocks "
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f"MC68450 Fig 4-25 sheet 4")
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print(f" v6 movem chain {B.V6_PX_CYC:.3f} clocks "
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f"MEASURED, FINDINGS 30")
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print(f" -> the DMAC is {100*(B.V6_PX_CYC-B.DMA_PX_CLK)/B.V6_PX_CYC:+.1f}% per pixel. "
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f"The 68000 writes in 4 clocks; the DMAC takes 5.")
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print(f" per span: DMAC array chaining {B.DMA_CHAIN_CLK} clocks against v6's "
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f"{B.V6_SPAN_CYC:.1f}\n")
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w = 15
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print(f"{'':<26}" + "".join(f"{n:>{w}}" for n, _ in DESIGNS))
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def row(label, fmt, get):
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print(f" {label:<24}" + "".join(f"{fmt(get(res[n])):>{w}}" for n, _ in DESIGNS))
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row("bitrate KB/s", lambda v: f"{v:.1f}", lambda r: r[2].mean() * a.fps / 1024)
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row("frame, median", lambda v: f"{v:.1f}%", lambda r: 100*np.median(r[0])/FRAME_CYC)
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row("frame, worst", lambda v: f"{v:.1f}%", lambda r: 100*r[0].max()/FRAME_CYC)
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row("frames missing", lambda v: f"{v}/{d.nframes}",
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lambda r: int((r[0] > FRAME_CYC).sum()))
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row("blocks spanned/frame", lambda v: f"{v:,.0f}", lambda r: r[3].mean())
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print(f"\n ADDITIVE: frame = CPU + span painting + disk DMA. The 68000 has no"
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f"\n cache and a two-word prefetch queue, so it stalls the moment another"
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f"\n master takes the bus. Disk debited at {a.disk_clk_word:g} clocks/word.")
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# What is left of the case, isolated.
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v6m = int((res["v6 span"][0] > FRAME_CYC).sum())
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finem = int((res["v6 fine tail"][0] > FRAME_CYC).sum())
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dmam = int((res["DMAC chain"][0] > FRAME_CYC).sum())
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print(f"\nWHAT THE DMAC ACTUALLY BUYS, decomposed")
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print(f" v6 as built {v6m}/{d.nframes} frames over")
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print(f" v6 with a finer chain tail (software) {finem}/{d.nframes}")
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print(f" DMAC chain {dmam}/{d.nframes}")
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print(f" -> of the gap between v6 and the DMAC, "
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f"{100*(v6m-finem)/max(v6m-dmam,1):.0f}% is the 24-pixel padding")
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print(f" quantum, which is a property of v6's unrolled chain and fixable")
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print(f" in software. The rest is 1.7% a pixel and 7.7 clocks a span.")
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# The additive model here IS FINDINGS 35's flat debit, and reproduces its
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# 84/120 exactly in the "today" column. Session 10's first pass replaced it with
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# max(CPU, bus) and got 53/120; that was wrong, because a 68000 cannot execute
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# while the DMAC holds the bus.
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print(f"\nbreak-even against all-V1 ({C_V1:.1f} cycles/block), clocks per block")
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print(f" {'L':<16}" + "".join(f"{L:>8}" for L in (1, 2, 3, 4, 8, 16, 64)))
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for nm, dz in (("v6 as built", "v6"), ("v6 fine tail", "v6fine"), ("DMAC chain", "dmac")):
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print(f" {nm:<16}" + "".join(f"{span_cost(dz, L)[1]/L:>8.0f}"
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for L in (1, 2, 3, 4, 8, 16, 64)))
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for nm, dz in (("v6 as built", "v6"), ("v6 fine tail", "v6fine"), ("DMAC chain", "dmac")):
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brk = next((L for L in range(1, 65) if span_cost(dz, L)[1] < L * C_V1), None)
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print(f" {nm:<16} beats all-V1 from L={brk} blocks up")
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