prosolis
c520a89e14
blit.s gains v7 -- v6's 24-pixel movem chain plus a second chain whose unit is
one `move.l (a0)+,(a2)+`. Measured over 13 span lengths by span.sh, every config
pixel-exact:
cycles = 66.0 per span + 9.143 per COARSE pixel + 9.978 per FINE pixel
fitting all 13 to within 0.2%. v5 and v6 re-measure to FINDINGS 30 exactly, so
the harness has not drifted underneath the new variant.
Rescored against the same scsi window and the same additive model, v7 takes
84/120 frames over budget to 18/120 -- exactly what FINDINGS 39.4 derived, and
that agreement is two cancelling errors: the derivation's 2-register movem tail
is 29% too dear per pixel, and its "nothing per span" for the second chain entry
is 22.3 clocks too cheap. The plain post-incrementing move.l is the right tail
instruction, and it makes the padding quantum 2 pixels, which a run of 4x4
blocks pads to exactly zero.
The DMAC stays dropped on a measurement now rather than an argument: v7 takes
back 37 of the 43 frames the array chain would, with no reserved channel and no
timing neither emulator here can verify. Break-even against all-V1 moves from
L=4 blocks to L=2.
The fine displacement is carried mid-stream rather than in the span record, so
the decoder holds nothing across the copy and keeps all 12 payload registers --
which is the whole reason the coarse unit is 24 pixels.
span.sh is now -seconds_to_run 200 (30 s wall, 36 configs) and takes its
expected snapshot count from the generated metadata instead of a literal 23.
Claude-Session: https://claude.ai/code/session_01194oWYW8DQXK1SZ2DnChW6
220 lines
10 KiB
Python
220 lines
10 KiB
Python
#!/usr/bin/env python3
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"""Would letting the HD63450 paint the spans beat letting the 68000 do it?
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python3 tools/analysis/14_dmac_chain.py [container.dlx] [--bus 488]
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[--dma-px-bus 2] [--disk-bus-byte 1]
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FINDINGS 29.6 called this the one lever that could move the CPU budget without
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spending a byte, and left it uncosted. FINDINGS 30 measured the alternative --
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the 68000 painting spans itself, 43.7 cycles per span + 9.152 per pixel. This
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prices the two against each other, and the answer turns on a resource neither
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section costed: the 68000's own LOCAL BUS.
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FINDINGS 29's "the bus has 4x the headroom the CPU has" is about the SCSI pipe,
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110 KB/s of 488. That is a different bus. The 68000's memory bus runs one 4-clock
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cycle at a time and carries instruction prefetch as well as data, and
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tools/analysis/15_bus_occupancy.py measures the decoder using 86.7% of it.
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THE TWO DESIGNS ARE THE SAME CONTAINER. v6's record is {u32 absolute GVRAM
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address, u16 jump displacement} = 6 bytes; an MC68450/HD63450 array-chaining
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entry is {u32 memory address, u16 transfer count} = 6 bytes. Set the channel to
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dual-address, direction device->memory, Sequence Control counting both addresses
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up: MAR reloads per entry (the GVRAM destination), DAR walks the stream buffer,
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MTC is the span's word count. The chain array IS the span table.
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THE DMAC CONSTANTS ARE NOW SOURCED, and they killed the first answer. From the
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MC68450 manual (Motorola, Jul 1989, bitsavers), Fig 4-25 sheet 4: a dual-address
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WORD operand between two 16-bit ports is **9 clocks**, because note 2 gives the
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DMAC 4-clock reads and **5-clock writes**. The 68000 writes in 4. So:
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DMAC 9.000 clocks/pixel (datasheet)
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v6 9.152 clocks/pixel (measured, FINDINGS 30)
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A 1.7% difference. Session 10's first pass guessed 2 bus cycles = 8 clocks from
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bus arithmetic and was 12% optimistic; the extra clock on every DMAC write is
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the whole story. Per span, sequential array chaining costs 36 clocks (Fig 4-25
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sheet 1) against v6's measured 43.7 -- the DMAC's one real edge, and it is small.
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AND DMA DOES NOT OVERLAP. The 68000 has no cache and a two-word prefetch queue,
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so it stalls as soon as another master takes the bus. Frame time is therefore
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CPU + DMA, additive. Session 10's first pass used max(CPU, bus) and got 53/120
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where the additive model gives 84/120; FINDINGS 35's flat debit was right.
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So the only material difference left is v6's 24-pixel padding quantum -- and
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that is a property of v6's unrolled chain, not of the CPU. The `v7 fine tail`
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column prices fixing it in software instead, and as of session 11 that column
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is MEASURED on the 68000 (blit.s v7, tools/bench/span.sh, FINDINGS 40) rather
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than derived: 66.0 clocks per span + 9.143 per coarse pixel + 9.978 per fine
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pixel, with a 2-pixel quantum that a run of 4x4 blocks pads to exactly.
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"""
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import sys, os, argparse
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sys.path.insert(0, "tools/encoder")
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sys.path.insert(0, "tools/analysis")
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import numpy as np
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from dlx import DLX
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import buscost as B
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FRAME_CYC = 833333.0
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AUDIO_KBPS = 7.8
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C_V1, C_V4, C_RAW = 299.9, 448.2, 400.4 # FINDINGS 28.2 (MEASURED)
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C_SKIP_CLUSTERED, C_SKIP_MIXED = 13.25, 45.0
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SPAN_BYTES_PX, SPAN_HDR = 2, 6
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ap = argparse.ArgumentParser()
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ap.add_argument("container", nargs="?", default="tmp/rc_fr_singe_scsi_cpufit.dlx")
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ap.add_argument("--bus", type=float, default=488.0, help="SCSI pipe, KB/s")
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ap.add_argument("--fps", type=float, default=12.0)
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ap.add_argument("--dma-px-clk", type=float, default=B.DMA_PX_CLK,
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help="clocks the DMAC spends per pixel, dual-address word "
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"between two 16-bit ports. 9 is the DATASHEET figure "
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"(MC68450 Fig 4-25 sheet 4).")
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ap.add_argument("--disk-clk-word", type=float, default=8.0,
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help="clocks the SCSI DMA steals per word. The datasheet "
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"brackets it at 5 (DMAC holds the bus) to 12 (arbitrates "
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"per word); FINDINGS 5's estimate of 8 is the midpoint.")
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a = ap.parse_args()
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if not os.path.exists(a.container):
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sys.exit(f"missing {a.container}")
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BYTE_BUD = (a.bus - AUDIO_KBPS) * 1024 / a.fps
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BUS_SLOTS = FRAME_CYC / B.BUS_CLK
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d = DLX(a.container)
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BLK_C = {1: C_V1, 2: C_V4, 3: C_RAW}
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BLK_B = {1: 1, 2: 4, 3: 16}
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def runs(m, by):
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dirty = m[by] != 0
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i = 0
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while i < d.nbx:
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if not dirty[i]:
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i += 1; continue
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j = i
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while j < d.nbx and dirty[j]:
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j += 1
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yield i, j
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i = j
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def span_cost(design, L):
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"""(pixels carried, clocks charged to the frame) for a run of L blocks,
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as 4 rows of 4L pixels. Every design is charged additively: the 68000
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cannot execute while the DMAC owns the bus."""
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if design == "v6":
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px = B.pad24(4 * L)
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return 4 * px, 4 * (B.V6_SPAN_CYC + px * B.V6_PX_CYC)
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if design == "v7":
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px, c = B.v7_span(4 * L)
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return 4 * px, 4 * c
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px = 4 * L
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return 4 * px, 4 * (B.DMA_CHAIN_CLK + px * a.dma_px_clk)
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def score(design):
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"""Greedy, as 12_span_tradeoff.py: buy the best clocks-saved per byte spent
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until the frame's byte budget is gone. Unlike 12, a spanned block still pays
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its mode-map dispatch, which FINDINGS 30.7 flagged as uncounted."""
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out = []
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for f in range(d.nframes):
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m = d.modes(f).reshape(d.nby, d.nbx)
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byt = d.mode_bytes + sum(BLK_B.get(int(x), 0) for x in m.ravel())
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spanned = np.zeros_like(m, bool)
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span_clk = 0.0
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cand = []
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if design != "none":
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for by in range(d.nby):
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for i, j in runs(m, by):
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L = j - i
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cur_c = sum(BLK_C[int(b)] for b in m[by][i:j])
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cur_b = sum(BLK_B[int(b)] for b in m[by][i:j])
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px, sc = span_cost(design, L)
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sc += L * C_SKIP_MIXED # the dispatch still happens
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# v7 carries a second u16 (the fine displacement) per span.
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hdr = B.V7_SPAN_HDR if design == "v7" else SPAN_HDR
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span_b = 4 * hdr + px * SPAN_BYTES_PX
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if sc < cur_c:
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cand.append((cur_c - sc, span_b - cur_b, by, i, j, sc, L))
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cand.sort(key=lambda s: -(s[0] / max(s[1], 1)))
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for dc, db, by, i, j, sc, L in cand:
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if byt + db <= BYTE_BUD:
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byt += db
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spanned[by][i:j] = True
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span_clk += sc - L * C_SKIP_MIXED
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g = m.copy()
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g[spanned] = 0
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gg = g.reshape(-1, 4)
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allskip = (gg == 0).all(1)
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cpu = allskip.sum() * 4 * C_SKIP_CLUSTERED
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mm = gg[~allskip]
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cpu += (mm == 0).sum() * C_SKIP_MIXED
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for k, c in BLK_C.items():
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cpu += (mm == k).sum() * c
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pref, data = B.block_bus(m, spanned)
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disk = byt / 2.0 * a.disk_clk_word
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# additive: CPU work, then span painting, then the disk stealing the bus
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out.append((cpu + span_clk + disk, (pref + data) * B.BUS_CLK, byt,
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spanned.sum()))
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return np.array(out).T
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DESIGNS = [("today", "none"), ("v6 span", "v6"),
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("v7 fine tail", "v7"), ("DMAC chain", "dmac")]
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res = {n: score(k) for n, k in DESIGNS}
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print(f"{a.container}: {d.nframes} frames, {d.nb} blocks, {a.fps:g} fps")
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print(f"SCSI pipe {a.bus:.0f} KB/s -> {BYTE_BUD:,.0f} B/frame; "
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f"68000 bus {BUS_SLOTS:,.0f} cycles/frame; CPU {FRAME_CYC:,.0f} clocks\n")
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print("PER PIXEL AND PER SPAN -- datasheet against measurement")
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print(f" DMAC dual-address word, two 16-bit ports {B.DMA_PX_CLK:.3f} clocks "
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f"MC68450 Fig 4-25 sheet 4")
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print(f" v6 movem chain {B.V6_PX_CYC:.3f} clocks "
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f"MEASURED, FINDINGS 30")
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print(f" -> the DMAC is {100*(B.V6_PX_CYC-B.DMA_PX_CLK)/B.V6_PX_CYC:+.1f}% per pixel. "
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f"The 68000 writes in 4 clocks; the DMAC takes 5.")
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print(f" per span: DMAC array chaining {B.DMA_CHAIN_CLK} clocks against v6's "
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f"{B.V6_SPAN_CYC:.1f}\n")
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w = 15
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print(f"{'':<26}" + "".join(f"{n:>{w}}" for n, _ in DESIGNS))
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def row(label, fmt, get):
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print(f" {label:<24}" + "".join(f"{fmt(get(res[n])):>{w}}" for n, _ in DESIGNS))
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row("bitrate KB/s", lambda v: f"{v:.1f}", lambda r: r[2].mean() * a.fps / 1024)
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row("frame, median", lambda v: f"{v:.1f}%", lambda r: 100*np.median(r[0])/FRAME_CYC)
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row("frame, worst", lambda v: f"{v:.1f}%", lambda r: 100*r[0].max()/FRAME_CYC)
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row("frames missing", lambda v: f"{v}/{d.nframes}",
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lambda r: int((r[0] > FRAME_CYC).sum()))
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row("blocks spanned/frame", lambda v: f"{v:,.0f}", lambda r: r[3].mean())
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print(f"\n ADDITIVE: frame = CPU + span painting + disk DMA. The 68000 has no"
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f"\n cache and a two-word prefetch queue, so it stalls the moment another"
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f"\n master takes the bus. Disk debited at {a.disk_clk_word:g} clocks/word.")
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# What is left of the case, isolated.
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v6m = int((res["v6 span"][0] > FRAME_CYC).sum())
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finem = int((res["v7 fine tail"][0] > FRAME_CYC).sum())
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dmam = int((res["DMAC chain"][0] > FRAME_CYC).sum())
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print(f"\nWHAT THE DMAC ACTUALLY BUYS, decomposed")
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print(f" v6 as built {v6m}/{d.nframes} frames over")
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print(f" v7, a finer chain tail (MEASURED) {finem}/{d.nframes}")
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print(f" DMAC chain {dmam}/{d.nframes}")
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print(f" -> of the gap between v6 and the DMAC, "
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f"{100*(v6m-finem)/max(v6m-dmam,1):.0f}% is the 24-pixel padding")
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print(f" quantum, which is a property of v6's unrolled chain and fixable")
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print(f" in software. The rest is 1.7% a pixel and 7.7 clocks a span.")
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# The additive model here IS FINDINGS 35's flat debit, and reproduces its
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# 84/120 exactly in the "today" column. Session 10's first pass replaced it with
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# max(CPU, bus) and got 53/120; that was wrong, because a 68000 cannot execute
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# while the DMAC holds the bus.
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print(f"\nbreak-even against all-V1 ({C_V1:.1f} cycles/block), clocks per block")
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print(f" {'L':<16}" + "".join(f"{L:>8}" for L in (1, 2, 3, 4, 8, 16, 64)))
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for nm, dz in (("v6 as built", "v6"), ("v7 fine tail", "v7"), ("DMAC chain", "dmac")):
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print(f" {nm:<16}" + "".join(f"{span_cost(dz, L)[1]/L:>8.0f}"
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for L in (1, 2, 3, 4, 8, 16, 64)))
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for nm, dz in (("v6 as built", "v6"), ("v7 fine tail", "v7"), ("DMAC chain", "dmac")):
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brk = next((L for L in range(1, 65) if span_cost(dz, L)[1] < L * C_V1), None)
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print(f" {nm:<16} beats all-V1 from L={brk} blocks up")
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